Event-Triggered DIAL Synchronization for Self-Timed Processors

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Solution Overview

Problem

Self-timed delay insensitive asynchronous logic (DIAL) blocks face challenges in synchronizing with external events efficiently, leading to unnecessary power consumption due to continuous cycling between propagate null and propagate data phases, especially when events are infrequent.

Innovation Solution

A process and circuit design that triggers a single propagate null and propagate data phase in response to an external event, utilizing a flip-flop to capture the event signal and a dual-rail DIAL block to synchronize operations, allowing the DIAL block to pause until an event occurs, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the DIAL block continuously cycles between propagate null and propagate data phases to ensure readiness for external events, then the system remains responsive to events, but power consumption increases unnecessarily

Engineering Contradiction:
Improveresponsiveness to external eventsVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system transitions from continuous periodic cycling to event-triggered periodic action. The DIAL block remains in a quiescent state and only activates periodic cycling when an external event occurs, thereby maintaining responsiveness while eliminating unnecessary power consumption during idle periods.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system uses the external event signal itself to trigger the propagation phases, eliminating the need for continuous internal clocking or periodic activation mechanisms. The event-driven architecture allows the system to serve itself by using external triggers to initiate operation only when needed.

Inventive Principle:
Principle #25Self-service

2Reliability

If the DIAL block operates continuously to maintain synchronization readiness, then event response capability is maintained, but operational efficiency decreases

Engineering Contradiction:
Improveevent response capabilityVSAvoidoperational efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system implements event-triggered periodic action where the DIAL block activates propagation phases only when external events occur. This maintains full event response capability while dramatically improving operational efficiency by eliminating continuous operation during idle periods.

Inventive Principle:
Principle #19Periodic action

3Use of energy by moving object

If the system uses a flip-flop to capture event signals and trigger single propagation phases, then power consumption is reduced, but circuit complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The flip-flop serves as an intermediary component that bridges the external event signal and the DIAL block propagation phases. This simple mediator element enables event-triggered operation with minimal added complexity, capturing the event signal and initiating the appropriate propagation phase only when needed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10326452B2Synchronizing a self-timed processor with an external event
Publication Date: 2019.06.18 SAMSUNG ELECTRONICS CO LTD
  • US10326452B2 patent drawing
  • US10326452B2 patent drawing
  • US10326452B2 patent drawing

AI summary

There is disclosed a self-timed processor. The self-timed processor includes trigger logic having a trigger input to receive an event trigger signal, a data input set to data value 1, a trigger output to send a trigger output signal when the event trigger signal is received, and a reset input to reset the trigger output signal. The processor also has a delay insensitive asynchronous logic (DIAL) block with multi-rail DIAL inputs to receive a multi-rail DIAL input having a) the trigger output signal, and b) data value 0; and data phase completion logic to output a completion signal indicating an end of a data propagate phase of the DIAL block to reset the trigger output signal when multi-rail data DIAL data process values of the DIAL block reach a DIAL valid state.