Embedded Wafer Level Package 3D Stacking via Interposer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packaging technologies face challenges in increasing density and reducing size while maintaining reliable connections and thermal management, particularly with issues related to thermal expansion mismatches and difficulties in forming through vias in molding compound layers.
Innovation Solution
The embedded wafer level package incorporates a redistribution layer on a support wafer with semiconductor dies and solder balls encapsulated in a molding compound, allowing for planarization and additional redistribution layers to create reliable electrical connections and a 3D stacking configuration, with the support wafer acting as an interposer for package-on-package configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias are formed in molding compound layers to create through-connections, then electrical connections can be established through the package, but the manufacturing process becomes extremely difficult and complex
Solution Approach 1:
The patent introduces a support wafer as an intermediary substrate that receives the semiconductor die and solder balls during packaging. This support wafer serves as a mediator that eliminates the need to form difficult through vias in the molding compound, while still enabling through-connections to be established through alternative, easier manufacturing processes on the support wafer itself
Solution Approach 2:
The patent segments the packaging process into distinct functional layers: the support wafer substrate, the molding compound encapsulation layer, and the redistribution layers. By separating the through-connection formation function from the molding compound layer and assigning it to the support wafer, the manufacturing difficulty is significantly reduced
2Productivity
If semiconductor devices are made smaller and more dense, then more devices can be made per wafer and products can be made more compact, but thermal management becomes more challenging due to thermal expansion mismatches
Solution Approach 1:
The patent changes the physical parameters of the support wafer, specifically selecting materials with thermal expansion coefficients that match or are compatible with the semiconductor die. This parameter adjustment resolves the thermal expansion mismatch problem while enabling higher device density and improved thermal management
3Area of stationary object
If fan-out wafer level packaging is used to increase area for back end processes, then contact positions can be relocated to larger footprint, but the original wafer real estate is sacrificed
Solution Approach 1:
The patent transitions from a 2D fan-out approach to a 3D vertical stacking approach. Multiple semiconductor dies are stacked vertically on the support wafer, with through-connections providing electrical pathways between layers. This dimensional change enables increased functionality and contact area without sacrificing horizontal wafer real estate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables increased density and compactness of semiconductor devices with reliable thermal management, reduced thermal stress due to matching thermal expansion, and efficient through connections, while avoiding the challenges of forming through vias in molding compound layers.
Implementation Method 1
The die and solder balls are encapsulated in a molding compound layer
Implementation Method 2
molding compound layer, which is planarized to expose top portions of the solder balls
Implementation Method 3
solder balls are also positioned on the redistribution layer in contact with electrical traces thereof
Implementation Method 4
The support wafer can act as an interposer layer for a package-on-package configuration, in which case the support wafer includes TSVs in electrical contact with the first redistribution layer on one side of the support wafer and an additional redistribution layer on the opposite side of the support substrate
Data Source
AI summary
An eWLB package for 3D and PoP applications includes a redistribution layer on a support wafer. A semiconductor die is coupled to the redistribution layer, and solder balls are also positioned on the redistribution layer. The die and solder balls are encapsulated in a molding compound layer, which is planarized to expose top portions of the solder balls. A second redistribution layer is formed on the planarized surface of the molding compound layer. A ball grid array can be positioned on the second redistribution layer to couple the semiconductor package to a circuit board, or additional semiconductor dies can be added, each in a respective molding compound layer. The support wafer can act as an interposer, in which case it is processed to form TSVs in electrical contact with the first redistribution layer, and a redistribution layer is formed on the opposite side of the support substrate, as well.