Exact Delay Synthesis for IC Timing Optimization
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Solution Overview
Problem
Current IC design tools face challenges in optimizing combinational logic circuits efficiently, leading to suboptimal timing performance due to unbounded arrival times and the exponential number of possible Boolean functions, which results in potential timing violations and increased design time.
Innovation Solution
The approach involves determining a logic function implemented by a combinational logic circuit, creating a permutation class representative, and applying a permutation to arrival time patterns to obtain an optimized circuit implementation by using an exact delay database lookup, ensuring globally optimal solutions by compressing arrival times and converting them into integer values for indexing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional IC design optimization methods are used, then design flexibility is maintained, but timing optimization performance is suboptimal due to unbounded arrival times and exponential Boolean function complexity
Solution Approach 1:
The patent transforms the continuous, unbounded arrival time parameters into discrete, bounded parameters by computing compressed arrival times using the formula: compressed_arrival_time = floor((arrival_time - min_arrival_time) / delay_precision). This parameter transformation reduces the infinite search space to a manageable finite space, enabling exact delay synthesis while maintaining timing optimization performance.
Solution Approach 2:
The patent creates a compressed representation (copy) of the original arrival time data that preserves all necessary timing information while reducing complexity. The compressed arrival times serve as a simplified model that enables exact delay lookup in pre-computed tables without losing the ability to achieve optimal timing results.
2Reliability
If exact delay synthesis with compressed arrival times is applied, then globally optimal circuit implementations are guaranteed, but additional processing steps are required for compression and permutation
Solution Approach 1:
The patent performs preliminary compression of arrival times and pre-computation of exact delay values stored in lookup tables before the actual optimization process. By pre-processing the arrival time data and pre-computing optimal delays for all possible compressed time patterns, the method guarantees globally optimal solutions while making the actual synthesis process efficient and manageable.
Solution Approach 2:
The patent introduces compressed arrival times as an intermediary representation between the original unbounded arrival times and the exact delay synthesis process. This intermediary form enables the use of pre-computed lookup tables and permutation-based optimization, bridging the gap between continuous timing data and discrete optimization algorithms.
3Productivity
If arrival times are compressed into bounded integers, then database lookup efficiency is improved, but information loss may occur
Solution Approach 1:
The patent changes the parameter representation from continuous unbounded arrival times to discrete bounded compressed arrival times using a mathematically rigorous compression formula. This transformation is designed to preserve all information necessary for timing optimization by maintaining the relative timing relationships and using the delay precision as the compression granularity, ensuring no critical timing information is lost.
Solution Approach 2:
The patent creates a compressed copy of the arrival time data that preserves all essential timing information needed for optimization. The compression process generates a simplified representation that maintains the relative ordering and timing differences between signals, enabling efficient database lookup without losing the ability to achieve optimal timing results.
Data Source
AI summary
Systems and techniques for optimizing an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. An optimized combinational-logic-cone can be obtained by performing, in addition to optionally other operations, a database lookup by using the logic-function identifier and the arrival-time-pattern identifier. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.