Exact-Match Flow Table Using Programmable Reduce Circuit
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Solution Overview
Problem
Existing packet switching technologies face inefficiencies in handling packets due to the lack of exact-match flow tables that can store wildcard indicators or mask values, leading to increased switching congestion and power consumption in network devices.
Innovation Solution
An integrated circuit with an exact-match flow table structure that uses Static Random Access Memory (SRAM) to store flow entries with unique Flow IDs, where each bit of the Flow ID is stored in one cell, and generates a Flow ID from incoming packets for bit-by-bit matching, with actions determined based on exact matches or miss indications, and includes a multiplexer circuit and programmable reduce table circuit for generating Flow IDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional flow tables with wildcard indicators and mask values are used, then packet matching flexibility is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and removes the wildcard indicator and mask value components from the flow table structure. By eliminating these elements, the flow table is simplified to store only exact Flow IDs, reducing structural complexity while maintaining packet matching capability through exact-match operations.
Solution Approach 2:
The patent changes the matching parameter from partial/wildcard matching to exact-bit matching. Each bit of the Flow ID is stored in one SRAM cell and matched exactly against corresponding packet bits, transforming the matching mechanism from complex pattern matching to simple exact comparison.
2Adaptability or versatility
If traditional flow tables with wildcard indicators are used, then packet matching versatility is improved, but power consumption increases
Solution Approach 1:
The patent removes wildcard indicators and mask values from the flow table, eliminating the computational overhead associated with evaluating these elements during packet matching. This extraction reduces power consumption while maintaining matching functionality through exact Flow ID comparison.
Solution Approach 2:
The patent uses simple SRAM cells for storing Flow ID bits, replacing complex matching structures with basic memory elements. Each SRAM cell stores one bit and participates in simple exact-match operations, reducing the energy cost per matching operation compared to traditional wildcard evaluation mechanisms.
3Productivity
If exact-match flow tables without wildcard indicators are used, then switching congestion is reduced, but packet handling adaptability decreases
Solution Approach 1:
The patent segments the packet handling process into two distinct phases: Flow ID generation from packet bits, and exact-match lookup of the generated Flow ID. This segmentation enables efficient exact-match switching while adaptability is maintained through the programmable Flow ID generation process that can extract different bit patterns from incoming packets.
Solution Approach 2:
The patent introduces the Flow ID as an intermediary between the incoming packet and the flow table lookup. The Flow ID is generated from selected packet bits through programmable logic, then used as the exact-match key. This intermediary enables efficient switching while maintaining adaptability through flexible Flow ID generation rules.
Data Source
AI summary
An exact-match flow table structure stores flow entries. Each flow entry includes a Flow Id. A flow entry is generated from an incoming packet. The flow table structure determines whether there is a stored flow entry, the Flow Id of which is an exact-match for the generated Flow Id. In one novel aspect, a programmable reduce table circuit is used to generate a Flow Id. A selected subset of bits of an incoming packet is supplied as an address to an SRAM, so that the SRAM outputs a data value. The data value is supplied to a programmable lookup circuit such that the lookup circuit performs a selected type of lookup operation, and outputs a result value of a reduced number of bits. A multiplexer circuit is used to form a Flow Id such that the result value is a part of the Flow Id.