Exact-Match Flow Table Structure for Packet Switching Efficiency
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Solution Overview
Problem
Existing packet switching technologies face inefficiencies in handling packets due to the lack of exact-match flow tables that can store wildcard indicators or mask values, leading to increased switching congestion and power consumption in crossbar switches, and require external processors for flow management.
Innovation Solution
An integrated circuit with an exact-match flow table structure that generates a unique Flow ID for packets, using SRAM to store flow entries without wildcard bits, and employs a multiplexer circuit and programmable reduce table to determine actions, reducing the need for external processors and minimizing crossbar switch load by storing non-flow specific and flow specific header information locally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional packet switching technologies are used without exact-match flow tables, then flow management requires external processors and wildcard indicators are needed, but this leads to increased switching congestion and power consumption in crossbar switches
Solution Approach 1:
The exact-match flow table structure enables the integrated circuit to perform flow management and packet switching autonomously without external processors. The circuit generates Flow IDs, performs exact-match lookups, and executes actions locally, making the system self-sufficient and eliminating the need for external flow management processors
Solution Approach 2:
The patent extracts the flow management functionality from external processors and embeds it directly into the integrated circuit's flow table structure. By removing wildcard indicators and mask values from the system and implementing pure exact-match flow tables, the patent simplifies the switching logic and reduces the computational burden on crossbar switches
2Ease of operation
If external processors are used for flow management, then flow control can be achieved, but this increases device complexity and switching congestion
Solution Approach 1:
The patent merges flow management functionality with the packet switching fabric by integrating exact-match flow tables directly into the crossbar switch structure. This consolidation eliminates separate external flow management processors and reduces system complexity while maintaining full flow control capabilities
Solution Approach 2:
The integrated circuit performs flow management autonomously using locally stored flow entries in the exact-match flow table. The circuit generates Flow IDs, performs lookups, and executes actions without external intervention, making the system self-sufficient and reducing architectural complexity
3Adaptability or versatility
If wildcard bits and mask values are stored in flow tables, then flexible packet matching is enabled, but this increases memory requirements and lookup complexity
Solution Approach 1:
The patent removes wildcard indicators and mask values from the flow table structure, implementing a pure exact-match flow table. Each flow entry contains only a Flow ID and associated action, eliminating the complexity of wildcard bit storage and mask value management while maintaining effective packet classification through exact-match Flow ID comparison
4Productivity
If header information is stored externally, then flow-specific processing can be performed, but this increases switching congestion and reduces packet handling efficiency
Solution Approach 1:
The patent extracts non-flow-specific header information from the packet switching path and stores it locally in the integrated circuit's memory. This extraction eliminates the need to repeatedly transmit header information across the switching fabric, reducing switching congestion and improving packet handling efficiency
Solution Approach 2:
The patent performs preliminary extraction and local storage of header information before packets enter the switching fabric. By preparing and caching header data in advance in the integrated circuit, the system avoids redundant header transmissions during packet switching, reducing traffic volume and improving efficiency
Data Source
AI summary
An integrated circuit includes a processor and an exact-match flow table structure. A first packet is received onto the integrated circuit. The packet is determined to be of a first type. As a result of this determination, execution by the processor of a first sequence of instructions is initiated. This execution causes bits of the first packet to be concatenated and modified in a first way, thereby generating a first Flow Id. The first Flow Id is an exact-match for the Flow Id of a first stored flow entry. A second packet is received. It is of a first type. As a result, a second sequence of instructions is executed. This causes bits of the second packet to be concatenated and modified in a second way, thereby generating a second Flow Id. The second Flow Id is an exact-match for the Flow Id of a second stored flow entry.