Hardware Exception Control Circuitry for Secure Domain State Saving
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Solution Overview
Problem
Existing data processing systems face a trade-off between security and performance, particularly in microcontrollers, where secure and non-secure domains require significant software intervention and overhead, compromising system efficiency.
Innovation Solution
A data processing apparatus with exception control circuitry that performs state saving of registers in hardware before triggering the exception handling routine, ensuring secure data is protected by performing additional state saving when transitioning from a secure to a non-secure domain, thereby preventing software modification of secure data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software exception handlers are used to protect secure data during domain transitions, then security is improved, but system performance and processing speed deteriorate due to increased software intervention overhead
Solution Approach 1:
The patent performs state saving of registers in hardware before the exception handling routine is triggered. This preliminary action ensures that secure data is already protected in memory before the domain transition occurs, eliminating the need for extensive software intervention during the critical transition period and thus maintaining both security and performance
Solution Approach 2:
The patent replaces software-based exception handling with hardware-based state saving mechanisms. The exception control circuitry automatically saves register states in hardware, substituting the slower software intervention with faster hardware operations, thereby improving system performance while maintaining security
2Reliability
If all register state is saved to data store during exceptions, then data integrity is improved, but processing time and overhead increase
Solution Approach 1:
The patent divides registers into two subsets: first subset registers whose state is automatically saved by exception control circuitry in hardware, and second subset registers whose state is saved by the exception handling routine in software. This segmentation allows critical data to be protected quickly by hardware while allowing less critical operations to be handled by software, balancing data integrity with processing time
Solution Approach 2:
The patent applies different state saving strategies to different register subsets based on their security requirements. The first subset registers (which may contain secure data) receive automatic hardware-based protection, while the second subset registers receive software-based protection, optimizing the balance between data integrity and processing overhead for each specific case
3Productivity
If exception control circuitry performs hardware state saving, then software intervention is reduced improving performance, but circuit area and hardware complexity increase
Solution Approach 1:
The exception control circuitry is designed to perform multiple functions: it automatically saves state from first subset registers, identifies when secure data is present, and triggers appropriate domain transitions. By consolidating these security-critical functions into a single hardware module, the patent reduces overall system complexity while maintaining high performance
Solution Approach 2:
The patent creates a hardware mechanism that copies register states to the data store structure, eliminating the need for complex software copying routines. This hardware copying capability simplifies the overall system architecture by replacing complex software logic with dedicated hardware functionality
4Reliability
If additional state saving is performed when transitioning from secure to non-secure domain, then security is maintained, but processing overhead increases
Solution Approach 1:
The exception control circuitry performs state saving of first subset registers before the domain transition is initiated. This preliminary hardware action ensures secure data is already protected in memory before the transition occurs, eliminating the need for additional security measures during the transition and reducing overall processing overhead
Solution Approach 2:
The exception control circuitry automatically performs state saving and domain transition management without requiring software intervention. This self-service capability ensures security is maintained while minimizing processing overhead, as the hardware handles all security-critical operations autonomously
Data Source
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Figure 3A~3B
AI summary
A data processing apparatus and method are provided for handling exceptions, the data processing apparatus having processing circuitry configured to perform data processing operations in response to program code, the processing circuitry comprising exception control circuitry for controlling exception processing. A plurality of registers are provided to store data, the registers including a first subset of registers and a second subset of registers, and a data store is also provided to store data, the data store comprising a plurality of regions including a secure region and a less secure region, wherein the secure region is for storing data which is accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain. In response to an initial exception from background processing performed by the processing circuitry, the exception control circuitry performs state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception, wherein the exception handling routine has responsibility for performing state saving of data from the second subset of registers. In response to a first exception causing a transition from the secure domain to the less secure domain, where the background processing was performed by the processing circuitry in the secure domain, the exception control circuitry performs additional state saving of the data from the second subset of registers before triggering the processing circuitry to perform the exception handling routine in the less secure domain. The hardware mechanism of the present invention enables effective handling of secure exceptions without requiring proxying through an exception handler.