Exception Interception for Secure Privilege Transitions

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Solution Overview

Problem

Current data processing systems face challenges in handling exceptions efficiently, particularly in scenarios where security and privilege levels are concerned, as they lack mechanisms to ensure secure transition between exception levels and prevent unauthorized access to sensitive data.

Innovation Solution

The implementation of exception interception and return trapping mechanisms, which allow for additional processing steps before entering the exception handler and secure restoration of processor state, by triggering further exceptions to a more privileged level when initial exceptions occur, enabling secure operations and data protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If exception handling is performed directly in the target exception level, then exception processing speed is improved, but security and privilege control are worsened due to lack of intermediate verification

Engineering Contradiction:
Improveexception processing speedVSAvoidsecurity and privilege control
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces an intermediate exception level (predetermined exception level) between the initial exception level and the target exception level. When exception interception is enabled, the system triggers a further exception to the predetermined exception level before allowing execution of the exception handler in the target exception level. This intermediary level acts as a mediator that performs security verification and privilege checks, ensuring that the transition between exception levels is secure while still allowing efficient exception handling to proceed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If exception interception is enabled to enhance security, then security control is improved, but system complexity is worsened due to additional exception handling steps

Engineering Contradiction:
Improvesecurity controlVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic exception handling where the system adapts its behavior based on the exception intercept configuration parameter. When exception interception is disabled, the system follows the simple direct path from initial exception to target exception level. When enabled, the system dynamically inserts an additional exception handling step at the predetermined exception level. This dynamic approach allows the system to maintain security capabilities while avoiding unnecessary complexity in scenarios where exception interception is not required.

Inventive Principle:
Principle #15Dynamics

3Reliability

If additional exception handling steps are inserted for security verification, then security is improved, but processing time is worsened

Engineering Contradiction:
Improvesecurity verificationVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs security verification and privilege checks in advance during the intermediate exception handling step at the predetermined exception level. By completing these security checks before the exception handler in the target exception level begins execution, the system ensures that security requirements are met without requiring additional verification steps during the main exception handling process. This preliminary action approach allows security to be enforced while minimizing the time impact on critical exception processing.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11216280B2Exception interception
Publication Date: 2022.01.04 ARM LTD
  • US11216280B2 patent drawing
  • US11216280B2 patent drawing
  • US11216280B2 patent drawing

AI summary

Exception control circuitry controls exception handling for processing circuitry. In response to an initial exception occurring when the processing circuitry is in a given exception level, the initial exception to be handled in a target exception level, the exception control circuitry stores exception control information to at least one exception control register associated with the target exception level, indicating at least one property of the initial exception or of processor state at a time the initial exception occurred. When at least one exception intercept configuration parameter stored in a configuration register indicates that exception interception is enabled, after storing the exception control information, and before the processing circuitry starts processing an exception handler for handling the initial exception in the target exception level, the exception control circuitry triggers a further exception to be handled in a predetermined exception level.