Exciter Clock Synchronization Using Modem Frame Pulse Feedback

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In HD Radio broadcasting systems, clock errors between the exporter and exciter devices can lead to synchronization issues, causing drift and requiring alternative methods for maintaining precise timing, especially when GPS signals are unreliable due to high RF noise.

Innovation Solution

A method and apparatus for synchronizing the exciter clock with a modem frame clock using voltage-controlled oscillators, counters, and loop filters to adjust the exciter clock signal based on timing errors, employing phase-locked loop techniques to achieve synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If GPS-locked 10 MHz clocks are used in both exporter and exgine to maintain synchronization, then clock synchronization is improved, but the system becomes vulnerable to high RF noise that disrupts GPS signals

Engineering Contradiction:
Improveclock synchronizationVSAvoidRF noise interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary synchronization method using modem frame pulses from the STL link as a mediator between the exporter and exgine clocks. Instead of directly relying on GPS signals at both locations, the system uses the STL communication link to transmit timing information (modem frame pulses) that serves as an intermediary reference, allowing the exgine to synchronize its clock without directly receiving GPS signals in the noisy RF environment.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the GPS-based electromagnetic timing system with an alternative synchronization mechanism based on counting modem frame pulses from the digital STL link. This substitution uses digital signal processing and pulse counting (mechanical/electronic counting mechanism) instead of relying on electromagnetic GPS signal reception, thereby avoiding vulnerability to RF noise while maintaining synchronization capability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of operation

If clock error difference of 1 ppm is tolerated, then system operation is simplified, but timing drift accumulates to 86.4 msec/day requiring frequent resynchronization

Engineering Contradiction:
Improvesystem operationVSAvoidtiming drift
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent implements a feedback mechanism where the exgine continuously monitors the timing of incoming modem frame pulses from the STL link and adjusts its local clock accordingly. By counting the pulses and comparing the actual timing against the expected timing, the system generates correction signals that feed back to the voltage-controlled crystal oscillator (VCXO) to maintain synchronization, thereby preventing cumulative timing drift without requiring overly strict initial clock accuracy.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically adjusts the frequency parameter of the exgine clock by using a voltage-controlled crystal oscillator (VCXO) whose frequency can be tuned in response to timing errors detected in the modem frame pulses. This parameter change capability allows the system to compensate for clock drift by changing the oscillator frequency, resolving the contradiction between operational simplicity and timing accuracy.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If a 44.1 kHz master clock is used to eliminate sample-rate-converter, then audio quality is improved, but the system requires precise clock synchronization to maintain single-clock-sample tolerance

Engineering Contradiction:
Improveaudio sampling accuracyVSAvoidclock synchronization stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent employs feedback control where the timing of modem frame pulses (which are synchronized to the 44.1 kHz audio sampling rate) is continuously monitored and used to adjust the exgine clock. This feedback mechanism ensures that the 44.1 kHz master clock remains synchronized between exporter and exgine, maintaining the required single-clock-sample tolerance for audio quality while ensuring reliability through continuous correction of any drift.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent uses periodic modem frame pulses as a reference rhythm to maintain synchronization. By aligning the exgine clock with the periodic arrival of these frames (which occur at the 44.1 kHz audio sampling rate), the system maintains precise timing without requiring overly complex continuous adjustment mechanisms, thereby achieving both audio quality and synchronization stability.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively synchronizes the exciter clock with the modem frame clock, reducing timing errors and maintaining accurate clock synchronization, even in environments with high RF noise, thereby ensuring reliable HD Radio broadcasting.

Implementation Method 1

producing an exciter clock signal... controlling the exciter clock signal in response to the count

Methodology Applied
Scientific EffectVoltage-controlled oscillation:

Implementation Method 2

controlling the exciter clock signal in response to the count... employing phase-locked loop techniques to achieve synchronization

Methodology Applied
Scientific EffectPhase-locked loop filtering: Feedback

Data Source

PatentUS7512175B2Method for synchronizing exporter and exciter clocks
Publication Date: 2009.03.31 IBIQUITY DIGITAL CORP
  • US7512175B2 patent drawing
  • US7512175B2 patent drawing
  • US7512175B2 patent drawing

AI summary

A method for synchronizing an exciter clock with a modem frame clock in a broadcasting system comprises the steps of receiving a plurality of modem frame pulses that are representative of the start of modem frames of audio signals and data signals, wherein timing of the modem frame pulses is controlled by a modem frame clock, producing an exciter clock signal, counting pulses representative of the exciter clock signal to produce a count representative of timing error of each incoming modem frame pulse, and controlling the exciter clock signal in response to the count. An apparatus that performs the method is also provided.