Exclusion Ring Assembly for Wafer Edge Deposition Uniformity
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Solution Overview
Problem
Achieving uniform semiconductor processing across the entire wafer surface, particularly at the edge regions, is challenging due to discontinuities that allow process gases to access the underside, leading to unwanted processing.
Innovation Solution
The use of an exclusion ring assembly comprising upper and lower annular rings with controlled gas flow passages and a pedestal with backside gas injection to manage gas flow and inhibit deposition at the edge, combined with selective exposure to deposition inhibitors and etchants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If process gases are allowed to flow freely across the wafer surface, then complete area coverage is achieved, but unwanted deposition occurs on the bevel edge and backside due to gas access through discontinuities
Solution Approach 1:
The exclusion ring assembly extracts and isolates the problematic edge region from the main processing area. By placing an annular exclusion ring at the wafer periphery, the system creates a physical barrier that extracts process gases from the edge region, preventing them from reaching the bevel edge and backside where unwanted deposition occurs, while maintaining processing in the central area
Solution Approach 2:
The system applies different gas flow conditions to different regions of the wafer. The exclusion ring creates a localized gas flow pattern where the edge region experiences reduced or directed gas flow compared to the central region. This local differentiation allows uniform deposition in the processed area while preventing harmful deposition at the edges
2Manufacturing precision
If the wafer edge region is excluded from processing to prevent unwanted deposition, then edge uniformity improves, but the processed area is reduced
Solution Approach 1:
The exclusion ring serves as an intermediary structure between the process gas source and the wafer edge region. Rather than completely excluding the edge region or allowing uncontrolled gas access, the intermediary ring structure mediates gas flow by directing it along the top surface while preventing access to the bevel and backside, thus achieving edge uniformity without significant area loss
3Quantity of substance
If gas flow passages are made wider to improve gas distribution, then gas flow increases, but gas may access the underside and cause unwanted processing
Solution Approach 1:
The exclusion ring assembly introduces a vertical dimension to gas flow control. By placing annular rings at different heights (upper and lower rings with a gap), the system creates a three-dimensional gas flow path that directs gas along the top surface in a controlled manner, preventing it from accessing the underside while maintaining adequate gas flow quantity for processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform film deposition up to the edge of the wafer, preventing unwanted deposition on the bevel edge and maintaining high uniformity within 1-3 mm of the edge, with non-uniformity less than 1% across the wafer.
Implementation Method 1
the upper annular ring is disposed over the lower annular ring to define an annular gas flow passage between the upper annular ring and the lower annular ring
Implementation Method 2
a pedestal with backside gas injection to manage gas flow and inhibit deposition at the edge
Implementation Method 3
selective exposure to deposition inhibitors and etchants
Data Source
AI summary
Provided herein are methods and apparatuses for controlling uniformity of processing at an edge region of a semiconductor wafer. In some embodiments, the methods include exposing an edge region to treatment gases such as etch gases and/or inhibition gases. Also provided herein are exclusion ring assemblies including multiple rings that may be implemented to provide control of the processing environment at the edge of the wafer.