Exclusion Zone Layout for Stress-Sensitive Analog Circuits
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Solution Overview
Problem
Integrated circuits, particularly those using 90 nm technology or below, are sensitive to stress, which affects their performance and reliability, and conventional methods to reduce stress, such as increasing die thickness or molding compound thickness, are impractical due to the demand for thin dies and require additional testing and debugging, increasing costs and time to market.
Innovation Solution
The method involves creating an exclusion zone on semiconductor chips to reduce stress effects on stress-sensitive circuits by fabricating these circuits outside high-stress regions, such as corner and edge areas, while maintaining compatibility with existing fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die thickness is increased to reduce stress effects, then stress sensitivity is reduced, but device miniaturization and integration density are compromised
Solution Approach 1:
The patent extracts stress-sensitive circuits from high-stress regions (corner regions where principal stresses exceed threshold values) by defining exclusion zones in the layout design. This spatial separation allows thin dies to be used while protecting sensitive circuits from stress effects.
Solution Approach 2:
The patent applies different design qualities to different regions of the chip: corner regions are designated as exclusion zones with restricted circuit placement, while non-corner regions allow normal circuit design. This local differentiation addresses stress sensitivity without compromising overall die thickness.
2Reliability
If molding compound thickness is increased to reduce stress, then stress effects are reduced, but packaging complexity and cost increase
Solution Approach 1:
The patent performs preliminary stress analysis during the circuit design phase to identify stress-sensitive circuits and define exclusion zones before fabrication. This upfront action prevents stress issues without requiring complex packaging modifications later.
3Reliability
If conventional stress reduction methods are applied, then stress sensitivity is reduced, but manufacturing cost and time to market increase due to additional testing and debugging
Solution Approach 1:
The patent performs preliminary stress analysis and defines exclusion zones during the design phase, before fabrication. This prevents stress issues from occurring in the first place, eliminating the need for subsequent testing and debugging activities.
Solution Approach 2:
The design methodology enables the circuit layout to self-protect against stress by automatically excluding sensitive circuits from high-stress regions through the exclusion zone framework, without requiring external testing or validation processes.
Data Source
AI summary
A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.