Executable Graph Sub-Graph Processing for Low-Latency Execution

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing n-tier architectures separate data storage from processing logic, leading to impedance mismatches and inhibiting flexibility, extensibility, and responsiveness, particularly in time-critical systems.

Innovation Solution

Executable graph-based models are decomposed into sub-graphs, integrating data and processing logic within a single model, allowing dynamic execution and separation when at rest, reducing processing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If data storage is separated from processing logic in n-tier architecture, then system modularity and maintainability are improved, but system flexibility, extensibility, and responsiveness deteriorate

Engineering Contradiction:
Improvesystem modularityVSAvoidsystem flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent merges data storage and processing logic into a unified graph-based model where both coexist in the same computational space. The graph model simultaneously represents data entities/relationships and processing operations, eliminating the traditional separation between data layer and processing logic layer, thereby achieving both modularity and flexibility.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The graph-based model serves multiple functions: it acts as both the data structure (storing entities and relationships) and the processing logic (through executable operations on graph nodes and edges). This universal model handles both data representation and computational operations, improving system adaptability while maintaining structural organization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Stability of the object's composition

If data storage is separated from processing logic in n-tier architecture, then clear separation of concerns is achieved, but processing delays increase due to impedance mismatch

Engineering Contradiction:
Improveseparation of concernsVSAvoidprocessing delays
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

By combining data and processing logic in the graph model, the patent eliminates the impedance mismatch that causes processing delays. Operations can directly access and manipulate graph data structures without requiring data transfer between separate storage and processing layers, significantly reducing latency in time-critical applications.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If entire graph-based model is loaded into memory for execution, then processing speed is improved, but memory resource consumption increases

Engineering Contradiction:
Improveprocessing speedVSAvoidmemory resources
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent segments the graph-based model into independent sub-graphs that can be selectively loaded into memory based on execution needs. Each sub-graph represents a modular unit of computation that can be loaded, executed, and unloaded independently, allowing the system to maintain high processing speed for active sub-graphs while minimizing overall memory consumption through selective loading.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically loads and unloads sub-graphs based on real-time execution requirements. Rather than statically loading the entire model, the system adapts memory usage by loading only the necessary sub-graphs into memory when needed and persisting others, optimizing the balance between processing speed and memory resource consumption.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12386898B2Systems and methods for sub-graph processing in executable graph-based models
Publication Date: 2025.08.12 INVERTIT INC
  • US12386898B2 patent drawing
  • US12386898B2 patent drawing
  • US12386898B2 patent drawing

AI summary

A method for dynamic execution of sub-graphs within executable graph-based models is provided. Processing circuitry obtains an executable graph-based model comprising a plurality of sub-graphs and an overlay structure comprising processing logic associated with the plurality of sub-graphs. Each sub-graph defines a hierarchical structure of related nodes. The processing circuitry receives a stimulus and a context associated with the stimulus. In response to the stimulus being received and based on the context, the processing circuitry maps the stimulus to a first sub-graph of the executable graph-based model. The processing circuitry causes execution of processing logic within the overlay structure based on the mapping. The processing logic is associated with one or more nodes of the first sub-graph.