Executable Thread Generation for Network Packet Processing
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Solution Overview
Problem
Conventional network processing architectures, relying on static ASICs or network processors, face inefficiencies due to contention for resources and inflexibility in packet processing, particularly in handling multiple threads accessing the same packet fields.
Innovation Solution
The development of a soft platform architecture for FPGAs that generates executable threads by adapting source code to only include referenced variables, allowing for efficient memory usage and flexible message processing through a programmable interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated network processors or ASICs are used for packet processing, then processing speed and reliability are improved, but flexibility and adaptability deteriorate due to static architecture
Solution Approach 1:
The patent implements dynamic thread creation and destruction capabilities, allowing the network processing system to adapt its architecture at runtime. Threads can be dynamically allocated to handle different packet processing tasks and terminated when no longer needed, enabling the system to flexibly respond to varying network conditions while maintaining reliable processing through structured thread management
2Productivity
If multiple processing elements access the same memory and interconnect resources, then processing capacity is improved, but resource contention increases reducing efficiency
Solution Approach 1:
The patent segments the packet processing functionality into multiple independent threads, where each thread handles specific packet processing tasks. This segmentation allows parallel processing of different packets or packet fields without requiring multiple processing elements to simultaneously access the same resources, thereby maintaining high processing capacity while reducing resource contention overhead
3Loss of information
If whole packets are stored in memory for processing, then complete packet information is available, but memory usage and access time increase
Solution Approach 1:
The patent extracts and processes only the specific packet fields that are relevant to the current processing task, rather than loading and accessing entire packets from memory. By identifying and extracting only the necessary data elements, the system maintains complete packet information when needed while significantly reducing memory access time and bandwidth requirements for typical processing operations
4Manufacturing precision
If processing elements access the same packet fields multiple times, then thorough processing is achieved, but access time and resource usage increase
Solution Approach 1:
The patent implements preliminary action by having threads identify and cache required packet fields before processing begins. By pre-identifying which fields need to be accessed and caching them in local storage, the system ensures thorough processing of all necessary fields while minimizing repeated memory accesses, thereby reducing overall access time without compromising processing completeness
Data Source
AI summary
From source code specification of each of a plurality of threads, those variables of a data structure referenced by the thread are determined. For each thread, a respective adaptation of the source code specification of the data structure is generated. Each adaptation includes only variables of the data structure that are referenced in the respective thread. The source code specifications of the threads are compiled into respective object code segments using the respective adaptations of the data structures. Each object code segment requires memory space for the data structure for only those variables included in the respective adaptation. The source code specification of the data structure describes a network packet, and the respective object code segments are configured to operate on the respective portions of the network packet stored in separate memories while executing on respective processors.