Execution Engine Spatial Tagging for Parallel Processing
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Solution Overview
Problem
General-purpose computers are inefficient in executing fine-grained parallel instructions, leading to high energy consumption and synchronization issues among processors, which is problematic for computationally intensive algorithms like sparse matrix solvers, signal processing, and data mining.
Innovation Solution
A computer system with a processing element that receives data tokens and matches them to instruction tokens based on spatial tags, using a spatial queuing system to manage contention and optimize energy and temporal performance, implemented in a data flow architecture with a processor fabric and streamers that transform data structures into tokens.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential instruction stream processors are used for fine-grained parallel computation, then processors can be coordinated through standard synchronization mechanisms, but energy consumption increases significantly and performance is limited to about 10% of peak capability
Solution Approach 1:
The patent segments the instruction stream into independent instruction tokens that can be executed in parallel across multiple processing elements. Each instruction token is dispatched independently to appropriate PEs based on spatial tags, eliminating the sequential execution bottleneck while reducing energy consumption by activating only the necessary subset of processors for each computation stage.
Solution Approach 2:
The patent introduces spatial tags as an additional dimension for instruction identification and routing. Instead of relying solely on temporal sequencing, instructions are tagged with spatial information that indicates their target processing elements. This spatial dimension enables simultaneous execution of instructions across different PEs without coordination overhead, dramatically improving throughput while reducing energy consumption.
2Productivity
If thousands of processors are used concurrently for fine-grained parallel computation, then computational performance improves, but synchronization time and energy consumption increase significantly
Solution Approach 1:
The patent extracts the synchronization mechanism from the execution process by eliminating the need for explicit synchronization barriers. Instruction tokens are dispatched independently to PEs based on their spatial tags, and processing elements automatically collect results when ready. This removes the synchronization step entirely, allowing thousands of processors to operate concurrently without time loss.
Solution Approach 2:
Processing elements autonomously manage their own execution and result collection based on spatial tags. Each PE independently executes assigned instructions and automatically makes results available to the instruction management unit when complete, eliminating the need for centralized coordination or synchronization barriers. This self-service approach enables concurrent processing of thousands of instructions without time loss.
3Adaptability or versatility
If general purpose processors are used for specialized algorithms like sparse matrix solvers, then hardware flexibility is maintained, but performance is limited to 10% of peak capability due to architectural mismatch
Solution Approach 1:
The patent implements dynamic instruction token generation and routing where the instruction management unit adapts the dispatching of instructions based on the specific algorithm being executed. Spatial tags are dynamically assigned to instruction tokens according to the computational pattern, allowing the same PE architecture to efficiently execute different algorithms like sparse matrix solvers, signal processing, and data mining without hardware reconfiguration.
Data Source
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AI summary
The execution engine is a new organization for a digital data processing apparatus, suitable for highly parallel execution of structured fine-grain parallel computations. Possible applications include many types of digital signal processing computations, such as filtering, convolution, and deconvolution, as well as many types of linear algebra operators, such as iterative and direct solvers, singular value decomposition, and constraint optimization. The invention improves energy efficiency of these structured parallel operators as compared to a regular data flow or von Neumann computer.