Execution Trace Module Dynamic Mode Switching
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Solution Overview
Problem
The increasing complexity of chip integration and power management in ASICs poses challenges for effective tracing and debugging, as existing standards like IEEE 1149.1 struggle to provide sufficient bandwidth for cycle-accurate tracing, especially in high-speed processors with multiple cores, leading to reduced debug pin budgets and power constraints.
Innovation Solution
The implementation of an execution trace module (ETM) that dynamically switches between cycle-accurate and non-cycle-accurate tracing modes, using an elastic FIFO buffer to manage bandwidth, allowing for extended tracing periods in lower bandwidth mode and temporary storage of excess data for later transmission during cycle-accurate mode, ensuring continuous program execution and accurate trace reporting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cycle-accurate tracing is implemented in high-speed processors, then measurement precision is improved, but bandwidth requirement increases beyond available capacity
Solution Approach 1:
The system dynamically adjusts tracing modes between cycle-accurate and non-cycle-accurate based on bandwidth availability. The execution trace module can switch between recording detailed cycle information and summarized trace information, allowing the tracing system to adapt its precision level to current bandwidth constraints while maintaining measurement capability when bandwidth permits.
Solution Approach 2:
The tracing system segments trace data into different types and priorities. Critical trace events are recorded with full cycle accuracy, while less critical events use compressed or summarized formats. This segmentation allows the system to allocate bandwidth selectively to different trace data categories, maintaining measurement precision for important events while reducing overall bandwidth consumption.
2Measurement precision
If tracing bandwidth is increased to maintain cycle-accurate tracing, then measurement precision is improved, but device complexity increases due to additional pins and power consumption
Solution Approach 1:
The execution trace module is designed to perform multiple functions through a single integrated unit. It can operate in both cycle-accurate tracing mode and non-cycle-accurate mode, and can also function as a general-purpose debug interface. This multi-functionality eliminates the need for separate dedicated high-bandwidth tracing pins, reducing pin budget requirements while maintaining tracing accuracy when needed.
Solution Approach 2:
The system changes operational parameters of the tracing interface dynamically. By adjusting the tracing mode between cycle-accurate and non-cycle-accurate, and by modifying data compression levels, the system can achieve different measurement precision levels using the same physical interface, thereby avoiding the need for additional pins or increased device complexity.
3Measurement precision
If tracing bandwidth is increased to maintain cycle-accurate tracing, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The tracing system dynamically adjusts its operational mode based on power availability and tracing requirements. The execution trace module can switch between power-intensive cycle-accurate tracing and power-efficient non-cycle-accurate tracing, allowing the system to optimize power consumption while maintaining measurement precision when power resources permit.
Solution Approach 2:
The system applies partial cycle-accurate tracing only when necessary for debugging critical issues, rather than continuously maintaining full cycle-accurate tracing. By using non-cycle-accurate mode for routine operation and switching to cycle-accurate mode only when needed, the system reduces overall power consumption while preserving the capability to achieve high measurement precision when required.
Data Source
AI summary
Systems and methods are provided in which two types of trace modes may be used at different times to trace events that occur during execution of an instruction program by a processor core. One such system includes execution trace circuitry that, when triggered, traces a sequence of events that occur during execution of the instruction program, and generates trace information indicative of the sequence of events. In response to a first trigger signal, the execution trace circuitry traces a first set of events in the sequence of events using a first trace mode, in which cycle information for the first set of events is not provided; and in response to a second trigger signal, the execution trace circuitry traces a second set of events in the sequence of events using a second trace mode, in which cycle information for the second set of events is provided.