Execution Trace TLB Logging for Address Omission and Obfuscation
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Solution Overview
Problem
Existing execution trace recording techniques result in large trace sizes due to logging full memory addresses, consuming significant processing, memory, and storage resources, and may expose sensitive information, making it difficult to reproduce undesired software behaviors and compromising security.
Innovation Solution
Implement memory address compression by logging translation lookaside buffer (TLB) entries instead of full memory page addresses, and optionally omitting or obfuscating physical memory addresses to reduce trace size and protect sensitive information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If full memory addresses are logged in execution traces, then complete memory access information is captured, but trace size increases significantly consuming processing, memory, and storage resources
Solution Approach 1:
The patent extracts only the necessary memory access information (virtual address and offset) while omitting redundant physical address information from execution traces. This selective extraction maintains the ability to reproduce software behaviors through virtual address translation while significantly reducing trace size and resource consumption.
Solution Approach 2:
The patent introduces virtual addresses as an intermediary representation between physical memory accesses and the trace recording system. By using virtual addresses instead of physical addresses, the system maintains complete memory access information for reproduction while avoiding the need to log full physical address specifications, thus reducing trace size.
2Loss of information
If full physical memory addresses are logged, then complete memory mapping information is recorded, but sensitive information is exposed
Solution Approach 1:
The patent extracts only virtual address information from memory accesses while omitting physical address information from execution traces. This selective extraction preserves the necessary memory mapping information for reproducing software behaviors while eliminating sensitive physical address data that could expose system security information.
Solution Approach 2:
The patent creates a virtual copy of memory address information (virtual addresses) that preserves the structural and functional characteristics needed for trace replay while lacking the sensitive physical address components. This virtual copy enables complete memory access information to be recorded without exposing sensitive physical memory mapping details.
3Measurement precision
If execution traces capture detailed memory cache influxes, then bit-accurate replay is enabled, but processing and storage resources are consumed excessively
Solution Approach 1:
The patent extracts only the essential memory access information (virtual address and offset) needed for bit-accurate replay while omitting redundant physical address details. This selective extraction maintains the precision required for accurate trace replay while significantly reducing the amount of data that must be processed and stored.
Solution Approach 2:
The patent changes the address representation parameter from physical addresses to virtual addresses in the trace recording system. This parameter change enables bit-accurate replay capability while reducing the information entropy and data volume required for trace storage and processing, thereby conserving resources.
Data Source
AI summary
Omitting or obfuscating physical memory addresses within an execution trace. A microprocessor identifies a first translation lookaside buffer (TLB) entry mapping a first virtual memory page to a physical memory page, and initiates logging of the first TLB entry by initiating logging of at least a first virtual address of the first virtual memory page and a first identifier. The microprocessor identifies a second TLB entry mapping a second virtual memory page to the physical memory page, and initiates logging of the second TLB entry by initiating logging of at least a second virtual address of the second virtual memory page and a second identifier. The microprocessor determines that the first and second TLB entries are each live, logged into the execution trace, and mapped to the same physical address, and ensures that the execution trace indicates that the first and second TLB entries each map to the physical address.