Execution Unit Opcode Splitting for Pipeline Throughput
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Solution Overview
Problem
Processing complex opcodes in processor execution units is inefficient due to internal dependencies, leading to increased chip area, power requirements, and decreased processing efficiency, as existing designs often require splitting instructions into multiple parts and waiting for one part to be completed before processing the other, resulting in bottlenecks and resource inefficiencies.
Innovation Solution
An integrated circuit with an execution unit featuring multiple pipelines and a scheduler unit configured with a 40 opcode queue, where each queue position supports up to four sources and a destination, allowing for the splitting of complex opcodes into load/store and simple opcode components and creating internal sources/destinations to facilitate efficient processing by utilizing both load/store and simple opcode support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex opcodes are processed by splitting into multiple parts and waiting for completion, then processing accuracy is improved, but processing speed deteriorates
Solution Approach 1:
The patent pre-allocates multiple queue positions for complex opcodes and prepares execution resources in advance. The scheduler identifies complex opcodes before execution and reserves necessary pipeline resources, eliminating waiting time during execution and enabling continuous processing without compromising accuracy.
Solution Approach 2:
The patent transitions from sequential single-pipeline processing to parallel multi-pipeline processing by allocating complex opcodes to multiple execution pipelines simultaneously. This dimensional change from time-sequential to space-parallel processing maintains processing accuracy while dramatically improving throughput and eliminating bottlenecks.
2Productivity
If dedicated pipeline queues are used for multi-pipeline execution, then processing speed is improved, but scheduling complexity increases
Solution Approach 1:
The patent implements a unified scheduler that can handle both simple and complex opcodes across multiple pipelines using the same scheduling logic and data structures. This universal approach maintains high processing speed through parallel execution while avoiding the complexity of separate scheduling mechanisms for different instruction types.
Solution Approach 2:
The patent segments the scheduling process into distinct phases: identification of complex opcodes, allocation of queue positions, and distribution to execution pipelines. This segmentation simplifies the overall scheduling complexity by breaking down the complex task into manageable, systematic steps that can be executed efficiently.
3Adaptability or versatility
If instructions are split into multiple parts for processing, then resource utilization is improved, but chip area increases
Solution Approach 1:
The patent ensures continuous utilization of execution pipelines by pre-allocating queue positions for complex opcodes and maintaining ready queues for both simple and complex instructions. This continuity allows pipelines to operate at full capacity without idle cycles, improving resource utilization without requiring additional chip area for buffer storage.
Solution Approach 2:
The patent merges the handling of simple and complex opcodes into a unified execution framework with shared queue structures and pipeline resources. By combining resource management for different instruction types into a single system, the patent achieves high resource utilization while minimizing the additional chip area that would result from separate dedicated structures.
Data Source
AI summary
Method and apparatus for fast decoding of microinstructions are disclosed. An integrated circuit is disclosed wherein microinstructions are queued for execution in an execution unit having multiple pipelines where each pipeline is configured to execute a set of supported microinstructions. The execution unit receives microinstruction data including an operation code (opcode) or a complex opcode. The execution unit executes the microinstruction multiple times wherein the microinstruction is executed at least once to get an address value and at least once to get a result of an operation. The execution unit processes complex opcodes by utilizing both a load/store support and a simple opcode support by splitting the complex opcode into load/store and simple opcode components and creating an internal source/destination between the two components.