Execution Unit Sharing Between Processor Cores in SoC Clusters

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Solution Overview

Problem

Modern processors with multiple cores suffer from reduced efficiency due to underutilization of processor cores and their associated execution units, leading to inefficiencies in computation time and power consumption.

Innovation Solution

A method for execution unit sharing between processor cores, where a structural hazard in an active processor core triggers a request for an idle execution unit from an inactive core, and the issued instruction is forwarded to the allocated EU with source operands and a result buffer address, replacing the instruction with a load operation to forward the result.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If processor cores are increased to handle more computations, then processing capacity is improved, but resource underutilization worsens leading to inefficiency

Engineering Contradiction:

Improveprocessing capacityVSAvoidcomputation time efficiency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent merges execution units from inactive processor cores with active processor cores by dynamically allocating idle execution units to handle instructions from active cores. This combining of resources allows underutilized execution units to be shared across multiple cores, improving overall resource utilization and reducing computation time without requiring additional hardware.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Execution units are designed to be universal resources that can serve multiple processor cores. The system enables execution units to dynamically switch between serving different cores based on demand, allowing the same execution unit to be allocated to different active cores as needed, thereby improving productivity while maintaining efficient resource utilization.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If execution units are allocated to active processor cores, then computation speed is improved, but power consumption increases

Engineering Contradiction:

Improvecomputation speedVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The system implements dynamic allocation of execution units based on real-time processor core activity. Execution units are activated and allocated to active processor cores only when needed, and deactivated when not in use. This dynamic approach allows the system to optimize computation speed by allocating resources on-demand while minimizing power consumption by keeping execution units in low-power states when not actively serving a core.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent ensures continuous useful action by maintaining a pool of idle execution units that can be quickly activated and allocated to active processor cores when computation is needed. This eliminates idle time for active cores while avoiding continuous operation of all execution units, thereby maintaining high computation speed efficiency while reducing overall power consumption through selective activation.

Inventive Principle:

Principle #20Continuity of useful action

3Productivity

If idle execution units are shared between cores, then resource utilization is improved, but system complexity increases

Engineering Contradiction:

Improveresource utilizationVSAvoidsystem complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary mechanism (execution unit allocation manager) that handles the complexity of sharing execution units between multiple processor cores. This intermediary layer manages the allocation, activation, and deactivation of execution units, abstracting the complexity from individual processor cores while improving overall resource utilization. The intermediary coordinates resource sharing without requiring complex changes to each core's internal architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12282447B2Execution unit sharing between processing cores in a cluster of a system-on-chip (SoC)

Publication Date: 2025.04.22 QUALCOMM INC

AI summary

A method of execution unit (EU) sharing between processor cores is described. The method includes encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core. The method also includes issuing a request for an idle execution unit of an inactive processor core. The method further includes sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core. The method also includes replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.