Expandable FPGA Logic Drive Using Bus Segmentation to Cut NRE
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Solution Overview
Problem
The transition from Field Programmable Gate Arrays (FPGA) to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips is hindered by high fabrication costs, larger chip size, higher power consumption, and lower performance, especially at advanced technology nodes, leading to a barrier for innovation and increased Non-Recurring Engineering (NRE) costs.
Innovation Solution
A standardized commodity logic drive utilizing plural FPGA IC chips and non-volatile memory IC chips, allowing for field programming and reducing NRE costs by using advanced technology nodes, enabling innovators to implement algorithms and applications at a fraction of the cost of traditional ASIC or COT chip development.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability and ease of operation are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The system divides the computing workload into distinct segments: volatile memory IC chips for active computation and non-volatile memory IC chips for persistent storage. This segmentation allows each component to be optimized independently, reducing overall system complexity while maintaining field programming capabilities through the non-volatile memory's ability to retain configuration data.
2Productivity
If ASIC or COT IC chips are used for volume applications, then manufacturing cost and performance are improved, but adaptability and ease of manufacture worsen
Solution Approach 1:
The system introduces dynamic reconfigurability through the combination of volatile and non-volatile memory IC chips. The non-volatile memory allows the system to be reconfigured between different algorithms and applications, providing adaptability similar to FPGA while achieving the performance and cost benefits of ASIC-like structures for volume applications. This dynamic capability enables the system to transition between specialized and general-purpose modes.
3Productivity
If advanced technology nodes are used for IC fabrication, then performance is improved, but Non-Recurring Engineering costs increase greatly
Solution Approach 1:
The system uses non-volatile memory IC chips to store configuration data and algorithm descriptions, effectively copying the functional behavior of complex ASIC designs into a reconfigurable medium. This allows advanced technology nodes to be utilized for high-performance computation while avoiding the high NRE costs of custom ASIC fabrication, as the same hardware can be reconfigured through software-like programming stored in the non-volatile memory.
Data Source
AI summary
An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.