Expandable FPGA Logic Drive Using Bus-Subset Interconnection
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Solution Overview
Problem
The transition from Field Programmable Gate Arrays (FPGA) to Application Specific Integrated Circuits (ASIC) or Customer-Owned Tooling (COT) chips is hindered by higher costs, power consumption, and lower performance, leading to increased Non-Recurring Engineering (NRE) costs for advanced semiconductor technology nodes, which limits innovation and adoption of advanced technology.
Innovation Solution
A standardized commodity logic drive utilizing plural FPGA IC chips and non-volatile memory IC chips, allowing for field programming and reducing NRE costs by enabling software development on existing hardware, similar to commodity DRAM or NAND flash memory businesses, and providing a public innovation platform for advanced IC technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability and ease of operation are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The system divides the computing workload into two segments: the FPGA IC chip handles logic control and coordination functions, while the non-volatile memory IC chip handles data storage and processing functions. This segmentation allows each component to be optimized independently, reducing the overall complexity and size requirements compared to a monolithic FPGA solution.
Solution Approach 2:
The non-volatile memory IC chip is designed to serve multiple functions: it acts as both storage memory and programmable logic resource. By utilizing the inherent programmability of non-volatile memory cells, the system achieves field programming capability without requiring a separate, complex FPGA fabric, thereby reducing device complexity while maintaining adaptability.
2Productivity
If ASIC or COT IC chips are used to expand application volume, then performance and power efficiency are improved, but Non-Recurring Engineering costs increase greatly
Solution Approach 1:
Instead of creating custom ASIC designs for each application, the system uses standard commodity non-volatile memory IC chips that can be copied and deployed repeatedly. The programmability of these standard chips allows different applications to be implemented by loading different firmware, eliminating the need for expensive custom mask sets and NRE investments while maintaining high performance.
Solution Approach 2:
The system changes the operational parameters of standard non-volatile memory chips through firmware programming to achieve application-specific optimization. This allows the same hardware platform to be adapted for different performance requirements without requiring physical hardware changes or expensive re-spinning of mask sets, thereby maintaining productivity while dramatically reducing NRE costs.
3Power
If advanced semiconductor technology nodes are adopted, then performance and power efficiency are improved, but NRE costs and fabrication complexity increase
Solution Approach 1:
The system uses universal standard non-volatile memory IC chips that can be manufactured at scale using established processes. These chips serve multiple applications through firmware programming, allowing the benefits of advanced technology nodes to be realized across many applications without requiring separate NRE investments for each application, thereby improving power efficiency while controlling fabrication costs.
Data Source
AI summary
An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.