Expandable Instruction Set Architecture for Dynamic Execution Resource Configuration
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Solution Overview
Problem
Processors with fixed execution resources and limited instruction sets lead to inefficiencies, as they cannot adapt to specific processing operations without risking improper operation or failure, limiting their ability to optimize performance for diverse applications.
Innovation Solution
A processor with an expandable instruction set architecture and a programmable execution unit (PEU) that allows dynamic configuration of execution resources, enabling software programmers to write hardware functional descriptions for specific operations, which are converted into programming information to program the PEU, thereby optimizing processing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a processor is manufactured with fixed execution resources and a standard instruction set, then manufacturing precision and reliability are improved, but adaptability to different applications deteriorates
Solution Approach 1:
The processor implements dynamic reconfiguration capabilities where execution resources can be programmatically adjusted after manufacturing. The PEU can be programmed with custom micro-operations that allow the processor to adapt its instruction set and execution behavior based on application requirements, transforming a static system into a dynamic one that maintains reliability while gaining versatility.
Solution Approach 2:
The processor incorporates a universal PEU that can perform multiple functions through programming. Instead of having dedicated hardware for each specific function, the PEU serves as a multi-functional unit that can be configured to execute different custom micro-operations, thereby providing adaptability across various applications while maintaining a compact design.
2Speed
If custom hardware blocks are added to perform specific processing operations, then processing speed is improved, but device complexity increases
Solution Approach 1:
Instead of adding separate custom hardware blocks for each processing operation, the patent uses a universal PEU that can be programmed to perform different functions. This single multi-functional unit replaces what would otherwise require multiple specialized hardware blocks, thereby achieving speed improvements for specific operations without proportionally increasing device complexity.
Solution Approach 2:
The processor achieves different processing capabilities by changing the programming parameters of the PEU rather than physically reconfiguring hardware. By loading different sets of custom micro-operations and control parameters, the same hardware structure can be optimized for different processing tasks, achieving speed improvements without adding structural complexity.
3Productivity
If the instruction set is expanded to include custom operations, then productivity is improved, but ease of operation deteriorates
Solution Approach 1:
The system introduces an intermediary layer consisting of custom micro-operations that serve as building blocks for application-specific instructions. These micro-operations provide a standardized interface between the programmer and the complex PEU configuration, allowing productivity improvements through optimized processing while maintaining ease of operation through a manageable programming model.
Solution Approach 2:
The processor performs preliminary configuration of the PEU by pre-defining custom micro-operations and their associated control parameters. This preliminary action prepares the execution unit in advance, allowing applications to leverage optimized processing without requiring programmers to manually configure complex hardware parameters, thereby maintaining ease of operation while achieving high productivity.
Data Source
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AI summary
A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.