Expandable Wired Network Device Tunnel Protocol Processing
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Solution Overview
Problem
Conventional Ethernet devices are inefficient in processing packets that comply with unsupported tunnel protocols, as they lack configurability and cannot execute operations such as decapsulation or encapsulation, limiting their ability to handle tunnel protocol information effectively.
Innovation Solution
A function-expandable wired network device is designed with an Ethernet device and an external circuit, where the Ethernet device receives and amends packets to direct them to the external circuit for processing, allowing the external circuit to decapsulate or encapsulate packets according to specific tunnel protocols, thereby overcoming the limitations of the Ethernet device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional Ethernet device receives a packet complying with an unsupported tunnel protocol, then the Ethernet device forwards the packet to an internal processor or external processor for processing, but this results in low processing efficiency
Solution Approach 1:
The patent segments the packet processing function into two parts: the Ethernet device handles standard Ethernet frame processing, while a separate external circuit (such as an FPGA or ASIC) handles tunnel protocol-specific processing. This segmentation allows each component to be optimized for its specific function, improving overall processing efficiency while maintaining adaptability to multiple tunnel protocols.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a customized Ethernet frame format that carries tunnel protocol information. This intermediary structure enables the Ethernet device to identify and forward tunnel packets to the external processing circuit without requiring the Ethernet device itself to understand or process the tunnel protocol, thus maintaining high processing efficiency.
2Adaptability or versatility
If an Ethernet device uses the header of an Ethernet packet to carry information about a tunnel protocol, then the Ethernet device can identify tunnel packets, but the conventional Ethernet device lacks configurability to transmit the packet to a processing circuit and cannot process packets that have been processed by an external circuit
Solution Approach 1:
The patent creates a universal packet processing architecture where the Ethernet device can handle both standard Ethernet packets and tunnel packets using the same hardware infrastructure. By embedding tunnel protocol identifiers in the Ethernet frame header and using configurable forwarding rules, the system achieves multi-functionality without increasing device complexity.
Solution Approach 2:
The patent changes the parameters of the Ethernet frame by adding or modifying header fields to carry tunnel protocol information. This parameter change enables the Ethernet device to identify and differentiate tunnel packets from standard packets, while the forwarding configurability allows flexible routing based on these modified parameters.
3Adaptability or versatility
If the Ethernet device forwards packets to external processors through non-Ethernet interfaces, then tunnel protocol processing can be performed, but this increases processing time and reduces efficiency
Solution Approach 1:
The patent merges the Ethernet device and the external processing circuit into a tightly coupled system where the external circuit (FPGA or ASIC) is directly connected to the Ethernet device's packet processing pipeline. This merging eliminates the need for time-consuming external interface conversions and allows inline processing of tunnel packets, significantly reducing processing time while maintaining protocol adaptability.
Data Source
AI summary
Disclosed is a function-expandable wired network device using an external circuit to execute an operation an Ethernet device can't execute. The wired network device includes an Ethernet switch and a Field-Programmable Gate Array (FPGA). The switch includes Ethernet ports including a designated port and a first port, and receives a first packet from the first port; and if the first packet carries information meeting the information prestored in the switch, the switch amends the first packet to output a second packet to the designated port. The FPGA receives the second packet from the designated port and processes the second packet according to the switch's amendment to the second packet so as to output a third packet to the designated port. The switch then processes the third packet according to the FPGA's amendment to the third packet to output a fourth packet to one of the Ethernet ports.