Expanded Landing Pads for DRAM Process Margin
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Solution Overview
Problem
As semiconductor memory devices, such as DRAMs, become more densely integrated, the process margin for forming patterns like conductive lands and storage nodes in the cell area decreases, making it challenging to maintain effective electrical connections and node placement.
Innovation Solution
The memory device design includes expanded landing pads and storage nodes, where each buried contact is positioned between gate and bit line stacks, with the expanded landing pads extending over adjacent bit line stacks and the storage nodes connected to these pads, ensuring a process margin and allowing for the same illumination system used in bit line formation to be applied to the landing pads, thus minimizing exposure processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional landing pads are used in densely integrated memory devices, then device integration is achieved, but process margin for forming patterns decreases and alignment precision deteriorates
Solution Approach 1:
The landing pad structure is segmented into two distinct types: conventional landing pads for standard connections and expanded landing pads for enhanced connections. This segmentation allows the device to simultaneously achieve high integration density while providing specific areas with increased process margin through the expanded pad geometry.
Solution Approach 2:
The expanded landing pads provide local quality enhancement by increasing the pad area and process margin in specific critical locations where additional tolerance is needed, while other areas maintain the conventional compact pad design to preserve overall device density and integration.
2Manufacturing precision
If expanded landing pads are used to increase process margin, then manufacturing precision is improved, but device area increases
Solution Approach 1:
Rather than uniformly expanding all landing pads across the device, the invention applies expanded landing pads only to specific locations where additional process margin is critically needed. This localized approach provides the necessary manufacturing precision improvement while minimizing the overall area increase, as most pads remain at conventional dimensions.
Solution Approach 2:
The landing pad array is segmented into conventional and expanded types, allowing the device to achieve improved process margin only where required by the expanded pads, rather than unnecessarily increasing the area of all pads. This selective application optimizes the balance between manufacturing precision and device area.
Data Source
AI summary
Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads.