Backside Power Via Structure for Dense Logic Cell Isolation
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Solution Overview
Problem
There is a need for semiconductor devices with improved integration density and reliability to meet the increasing demand for high-performance and multi-functional semiconductor devices, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor device design that includes a substrate with dummy regions, device isolation layers, power lines with expanded portions, and through vias connecting the power delivery network to these lines, allowing for efficient voltage application and reduced electrical influence on neighboring logic cells, thereby enhancing integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased to meet demand for high-performance semiconductor devices, then device functionality and performance improve, but electrical interference between neighboring cells increases and reliability deteriorates
Solution Approach 1:
The patent introduces dummy regions and device isolation layers as intermediary structures between neighboring logic cells. These isolation structures act as mediators that block electrical interference while allowing the power delivery network to function effectively, thus enabling high integration density without compromising electrical stability
Solution Approach 2:
The patent applies different structural qualities to different regions: logic cells contain active transistors for computation, while dummy regions contain only isolation structures for electrical separation. This local differentiation allows neighboring cells to be closely spaced without interference, improving integration density while maintaining reliability
2Adaptability or versatility
If power delivery network is extended to supply voltage to all cells, then device functionality improves, but voltage drop and electrical interference increase
Solution Approach 1:
The patent segments the power delivery by providing separate power lines for logic cells and dummy regions, with isolated power delivery networks for each segment. This segmentation prevents voltage drops and electrical interference from propagating across the entire device, allowing extensive power distribution while maintaining voltage stability
Solution Approach 2:
Device isolation layers serve as intermediaries that separate the power delivery networks of neighboring cells. This isolation prevents electrical interference between cells while allowing each cell to receive stable voltage through its own dedicated power lines
3Reliability
If dummy regions are added to reduce electrical interference, then reliability improves, but device area and complexity increase
Solution Approach 1:
The dummy regions serve multiple functions: they provide electrical isolation between neighboring logic cells, acts as placeholders for future cell expansion, and maintain regular device geometry. This multi-functionality achieves reliable electrical isolation without proportionally increasing device complexity
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.