Expanded Semiconductor Chip Electrode Relocation
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased sensitivity of transistors to thermal stress during packaging, causing variations in source/drain current and potential damage from low-k insulating materials, which are mechanically weak and prone to cracking or peeling.
Innovation Solution
A semiconductor device configuration featuring an expanded portion on at least one side surface of a semiconductor chip with electrodes only on this expanded portion, allowing electrical connection to external elements while avoiding electrodes on the element formation surface, thereby reducing thermal stress impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If electrodes are provided on the element formation surface of the semiconductor chip for electrical connection, then electrical connection to external elements is achieved, but thermal stress during packaging causes large variation in source/drain current of transistors
Solution Approach 1:
The patent relocates electrodes from the element formation surface (top dimension) to the side surface of the semiconductor chip (lateral dimension). This dimensional shift allows electrical connection to be achieved while avoiding the thermal stress concentration area on the element formation surface, thereby maintaining transistor electrical characteristics.
Solution Approach 2:
The patent introduces an expanded portion as an intermediary structure that extends from the side surface of the semiconductor chip. This expanded portion serves as a mediator that provides electrode mounting area away from the element formation surface, reducing direct thermal stress impact on active elements while enabling external electrical connection.
2Speed
If low-k insulating materials are used in multilevel interconnect layers to match transistor miniaturization, then higher data transfer rate is achieved, but cracks are generated in the insulating layer or peeling occurs at the interface during packaging
Solution Approach 1:
The patent extracts the electrodes from the element formation surface where they would subject low-k insulating layers to thermal stress during packaging. By relocating electrodes to the side surface via expanded portions, the source of thermal stress is removed, preventing crack generation and interface peeling in the mechanically weak low-k insulating materials.
3Ease of operation
If semiconductor chips are packaged with electrodes on the element formation surface, then electrical connection is established, but residual stress upon solder solidification causes large variation in transistor characteristics
Solution Approach 1:
The patent moves electrodes from the element formation surface to the side surface of the chip, changing the spatial dimension of connection. This relocation eliminates the thermal stress pathway from solder bumps through the element formation surface to the transistor regions, maintaining consistent transistor characteristics during packaging while achieving electrical connection.
Data Source
AI summary
A semiconductor device includes: a first semiconductor chip having a surface provided with first electrodes; and an expanded semiconductor chip including a second semiconductor chip and an expanded portion extending outward from at least one side surface of the second semiconductor chip. The expanded semiconductor chip has a surface provided with second electrodes. The surface of the first semiconductor chip provided with the first electrodes faces the surface of the expanded semiconductor chip provided with the second electrodes so that the first electrodes are connected to the second electrodes. Each one of the second electrodes that is connected to an associated one of the first electrodes is located only on the expanded portion.