Expanded Semiconductor Chip for High-Density Interconnects
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Solution Overview
Problem
The existing chip-on-chip (CoC) technique faces challenges in forming a suitable re-distribution structure when the lower chip is smaller than the upper chip, particularly in achieving accurate and high-density interconnects due to constraints in the pitch of connecting portions and the complexity of exposing conductive members for electrical connection.
Innovation Solution
The solution involves forming an expanded semiconductor chip by adding an expanded portion around the outer edge of the lower chip, which includes a re-distribution structure that electrically connects the upper chip to the lower chip without interposing conductive members, allowing for connection terminals to be connected via wire bonding, and using a resin material with lower resolution for the re-distribution lines to simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of CoC connecting portions is reduced to achieve higher-density interconnects, then the quantity of connections increases, but the manufacturing precision and exposure accuracy become more difficult to achieve
Solution Approach 1:
The patent divides the connection structure into two distinct parts: CoC connecting portions (microbumps) for chip-to-chip connections, and wire bonding portions for chip-to-substrate connections. This segmentation allows each part to be optimized independently, enabling reduced pitch for CoC connections without compromising the manufacturability of wire bonding portions.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the CoC connecting portions have reduced pitch for high-density interconnects, while the wire bonding portions maintain larger dimensions for ease of manufacturing. The insulating resin material is selectively positioned to cover only the wire bonding portions, preserving the electrical connection functionality of both regions with appropriate local properties.
2Area of stationary object
If the lower chip is made smaller than the upper chip to optimize system layout, then the area of the lower chip is reduced, but conductive members cannot be physically drawn from connection terminals by simple connection methods
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical connections using microbumps for CoC interconnects. This dimensional change allows the lower chip to be smaller while maintaining electrical connectivity, as the microbumps provide direct vertical pathways through the insulating resin material, eliminating the need for lateral conductive member drawing.
Solution Approach 2:
The insulating resin material serves as an intermediary that fills the space between the lower chip and upper chip, providing both mechanical support and electrical isolation. Embedded within this resin are the CoC connecting portions that act as conductive pathways, enabling connections without requiring conductive members to be drawn from the lower chip's connection terminals.
3Reliability
If the periphery of microbumps is entirely covered by resist to protect connection portions, then the protection and accuracy of connecting portions is improved, but the exposure of resist opening becomes a constraint on performing re-distribution
Solution Approach 1:
The patent extracts the insulating resin material application from the entire chip surface and applies it selectively only to the wire bonding portions. This extraction eliminates the need for complex resist opening exposure processes around microbumps, as the resin naturally provides protection without requiring additional photolithography steps that would constrain re-distribution design.
Data Source
AI summary
A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.