Expanded Semiconductor Chip for Flexible Chip Stacking
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Solution Overview
Problem
Conventional semiconductor devices with a chip-on-chip structure are limited by chip size, making it impossible to stack a logic circuit chip equivalent to or larger than a memory chip, which increases costs and reduces the number of chips per wafer.
Innovation Solution
A semiconductor device with an expanded semiconductor chip that includes a first semiconductor chip and an extended portion on its side surface, allowing for chip-on-chip connection with a second semiconductor chip and flip-chip mounting on a base, without size limitations, using bumps and re-distribution interconnects for efficient interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory chip larger in size than the logic circuit chip is used to enable chip-on-chip stacking, then the chip stacking becomes possible, but the number of chips per wafer decreases and manufacturing costs increase
Solution Approach 1:
The invention introduces an expanded portion that protrudes from the side surface of the logic circuit chip in the width direction, creating a three-dimensional structure. This allows the connection surface area to be enlarged without increasing the planar chip size, enabling chip-on-chip stacking regardless of the relative sizes of the logic circuit chip and memory chip, while maintaining high chip density per wafer
2Reliability
If conventional flip-chip connection is used for chip-on-chip stacking, then connection between chips is achieved, but size limitation is imposed where the memory chip must be larger than the logic circuit chip
Solution Approach 1:
By adding the expanded portion that protrudes from the side surface, the invention creates an asymmetric three-dimensional structure. This allows the connection surface to accommodate chips of any relative sizes, eliminating the conventional limitation where the memory chip must be larger than the logic circuit chip, while maintaining reliable bump connections
3Ease of manufacture
If the logic circuit chip is made equivalent to or larger than the memory chip to reduce manufacturing costs, then cost reduction is achieved, but chip-on-chip stacking becomes impossible with conventional methods
Solution Approach 1:
The expanded portion protruding from the side surface creates additional connection area in the width direction, allowing the logic circuit chip to be equivalent to or larger than the memory chip while still enabling chip-on-chip stacking. This eliminates the need to use unnecessarily large memory chips, reducing manufacturing costs while maintaining stacking capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables flexible stacking and mounting of semiconductor chips regardless of size, reducing manufacturing costs and increasing chip density, while maintaining high processing speed and functionality.
Implementation Method 1
a plurality of first bumps which connect the first semiconductor chip and the second semiconductor chip to each other; and a plurality of second bumps which connect the expanded portion and the base to each other
Data Source
AI summary
A semiconductor device includes an expanded semiconductor chip having a first semiconductor chip and an expanded portion extending outward from a side surface of the first semiconductor chip, a second semiconductor chip provided so as to be connected to the expanded semiconductor chip via a plurality of first bumps, and a base provided so as to be connected to the expanded semiconductor chip via a plurality of second bumps. The first bumps are provided between the first semiconductor chip and the second semiconductor chip. The second bumps are provided between the expanded portion and the base.