Expanded Via SRAM Connection Layout for Lower Capacitance
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Solution Overview
Problem
The challenge in integrating SRAM cells with microprocessors is the need for additional masks and process steps due to differences in manufacturing processes, leading to alignment errors, increased cell size, and high capacitance, which affects performance and storage reliability.
Innovation Solution
A compact SRAM cell layout using expanded vias that connect multiple contacts and gates, eliminating the need for additional masks by utilizing the same process steps as the microprocessor, reducing alignment errors and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If additional masks and process steps are used for SRAM cell manufacturing, then the SRAM cell can be manufactured with separate process steps, but the manufacturing complexity and alignment errors increase
Solution Approach 1:
The patent combines SRAM cell manufacturing with microprocessor manufacturing by using the same masks and process steps for both. The SRAM cell structures are integrated into the microprocessor fabrication sequence, eliminating separate manufacturing processes and reducing overall complexity.
Solution Approach 2:
The patent makes the microprocessor manufacturing process universal by designing it to simultaneously create both microprocessor circuits and SRAM cell structures. The same masks and process steps serve dual purposes, making the manufacturing process applicable to multiple device types.
2Manufacturing precision
If additional masks are used for SRAM cell manufacturing, then the SRAM cell can be manufactured with dedicated process steps, but the alignment errors increase
Solution Approach 1:
The patent merges SRAM cell mask patterns with microprocessor mask patterns, so that the same masks define both microprocessor circuit features and SRAM cell features. This eliminates additional alignment operations and reduces cumulative alignment errors.
3Reliability
If larger cell size is used, then the SRAM cell can accommodate separate manufacturing processes, but the capacitance increases affecting performance
Solution Approach 1:
The patent transitions from planar metal wiring connections to vertical via-based connections. By moving connections to different vertical layers and using expanded vias that extend through insulating layers, the design reduces parasitic capacitance associated with planar metal traces while maintaining reliable data storage.
4Productivity
If separate process steps are used for SRAM cell manufacturing, then the SRAM cell can be manufactured independently, but the total manufacturing time increases
Solution Approach 1:
The patent combines SRAM cell manufacturing steps with microprocessor manufacturing steps into a single integrated process sequence. Multiple structures are formed simultaneously using the same deposition, etching, and patterning operations, eliminating sequential processing delays.
Data Source
AI summary
An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.