Expansion Bridge Chip Modular Interface Routing

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Solution Overview

Problem

The existing modular chip architecture limits the interconnection of modules in systems-on-multiple-modular-chips due to a fixed number of upstream and downstream interfaces, making it difficult to connect more peripherals than an application processor can natively support.

Innovation Solution

The introduction of an expansion bridge chip with multiple upstream and downstream interfaces, including an upstream address decoder and optional downstream address decoders, allows for increased connectivity by routing signals between modules and buffering data, enabling the connection of more peripherals than the application processor's native interfaces allow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a fixed number of upstream and downstream interfaces are provided on each modular chip, then the chip structure remains simple and manageable, but the system's connectivity and adaptability are limited

Engineering Contradiction:

Improveinterface connectivityVSAvoidchip structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The expansion bridge chip serves as an intermediary device between the application processor and multiple peripheral modules. It receives data from the application processor through its upstream interface, decodes addresses to determine the destination, and routes the data through appropriate downstream interfaces to the target peripheral modules. This mediator approach enables extended connectivity without requiring the application processor itself to have additional native interfaces.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system is segmented into distinct functional components: the application processor, the expansion bridge chip, and multiple peripheral modules. The expansion bridge chip is further segmented with separate upstream and downstream interfaces, allowing independent optimization of each interface's connectivity characteristics. This segmentation enables the system to achieve high adaptability while maintaining manageable complexity in each individual component.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If more downstream interfaces are added to connect additional peripheral modules, then the system's versatility increases, but the bandwidth available to each interface must be reduced

Engineering Contradiction:

Improveperipheral connectivityVSAvoidinterface bandwidth

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The expansion bridge chip implements dynamic bandwidth allocation where the upstream interface can operate at high speed to receive data from the application processor, while downstream interfaces dynamically share this bandwidth based on actual communication needs. The address decoder and buffering mechanisms enable multiple downstream interfaces to access the upstream bandwidth efficiently, allowing the system to maintain high overall throughput while supporting multiple peripherals.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The expansion bridge chip includes buffering capability that performs preliminary action by temporarily storing data received from the application processor before routing it to the appropriate downstream interface. This buffering allows the upstream interface to operate independently at its full bandwidth capacity while downstream interfaces access data at their respective speeds, decoupling the bandwidth constraints between upstream and downstream connections.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If address decoding is implemented on downstream interfaces to enable signal routing between downstream modules, then the flexibility of inter-module communication increases, but the device complexity increases

Engineering Contradiction:

Improvesignal routing flexibilityVSAvoiddecoder configuration

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Address decoding capability is applied locally at the expansion bridge chip where it is most needed for routing purposes. The upstream address decoder handles the primary routing function from the application processor to downstream modules. Optional downstream address decoders are provided only where needed to enable specific downstream-to-downstream communication paths, allowing the system to achieve necessary routing flexibility while minimizing the overall complexity by implementing decoding only where required rather than universally across all interfaces.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10459868B1Modular chip expansion bridge and corresponding methods

Publication Date: 2019.10.29 MARVELL ASIA PTE LTD

AI summary

An expansion bridge chip for a modular chip system includes at least one upstream interface for communicating with an application processor module, a plurality of downstream interfaces for communicating with peripheral modules, and an upstream address decoder on each interface for directing data on the upstream interface to a downstream interface. In such an expansion bridge chip, each upstream interface may have a first bandwidth, each downstream interface may have a respective bandwidth, and the expansion bridge chip may be balanced, such that a sum of all respective bandwidths of the plurality of downstream interfaces is equal to the first bandwidth. Alternatively, each upstream interface may have a first bandwidth, each of the downstream interfaces may have a respective bandwidth, and the expansion bridge chip is unbalanced, such that a sum of all respective bandwidths of the plurality of downstream interfaces exceeds the first bandwidth, and interfaces contend for bandwidth.