Expansion Tape Stretching for Precise Semiconductor Chip Spacing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing methods for expanding the interval between semiconductor chips using expansion tapes often result in position aberration of the chips, leading to potential damage during dicing and decreased productivity.

Innovation Solution

A method involving a transferring expansion tape that is heated and stretched at a controlled expansion rate between 100% and 300% per expansion, with a stress-strain curve ensuring minimal position aberration, and repeated tape expanding and transferring steps to achieve the desired interval without significant chip displacement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the expansion tape is stretched to expand the interval between semiconductor chips, then the interval between chips is increased, but position aberration of the semiconductor chip occurs

Engineering Contradiction:
Improveinterval between chipsVSAvoidposition aberration of chip
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The expansion process is divided into multiple sequential steps, each with a controlled expansion rate between 100-300%. By segmenting the total expansion into multiple smaller increments rather than one large expansion, the position aberration is reduced while still achieving the desired final interval between chips.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The expansion tape is prepared in advance with specific stress-strain characteristics that ensure minimal position aberration during expansion. The tape's mechanical properties are pre-selected and controlled so that when expansion is performed at the specified rate, the semiconductor chips maintain their positional accuracy.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the expansion rate is increased to improve productivity, then the expansion process is faster, but position aberration increases

Engineering Contradiction:
Improveexpansion speedVSAvoidposition aberration of chip
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The expansion rate parameter is optimized to a specific range (100-300%) that balances productivity and precision. This parameter change ensures that the expansion proceeds quickly enough for practical manufacturing while maintaining position aberration at acceptable levels. The stress-strain characteristics of the expansion tape are also adjusted to match this expansion rate.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively suppresses position aberration of semiconductor chips during interval expansion, ensuring reliable dicing and maintaining productivity by using a predetermined expansion tape with specific properties to manage stress and strain.

Implementation Method 1

a tape expanding step of stretching a transferring expansion tape while heating to expand an interval between a plurality of semiconductor chips fixed onto the transferring expansion tape

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

a stress-strain curve obtained by a tensile test in an MD direction and a TD direction under a heating temperature in the tape expanding step

Methodology Applied
Scientific EffectElasticity: Elasticity

Data Source

PatentUS20250014937A1Method for manufacturing semiconductor device
Publication Date: 2025.01.09 RESONAC CORP
  • US20250014937A1 patent drawing
  • US20250014937A1 patent drawing
  • US20250014937A1 patent drawing

AI summary

A method for manufacturing a semiconductor device includes a tape expanding step of stretching an expansion tape while heating to expand an interval between a plurality of semiconductor chips fixed onto the expansion tape at an expansion rate in a range A per one expansion, a transferring step of transferring the plurality of semiconductor chips to an expansion tape, and repeating the tape expanding step and the transferring step. In a stress-strain curve according to a tensile test of the expansion tape, an elongation range B in which an absolute value of a difference between a MD tensile stress and a TD tensile stress is 2.8 MPa or less overlaps with a part of the range A. The tape expanding step includes expanding the interval by using an elongation value selected from an overlapping range between the range A and the range B as the expansion rate per one expansion.