Explicit Dependency Keys for Persistent Memory Ordering
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Solution Overview
Problem
In computing systems, especially with the advent of non-volatile main memory (NVMM), there is a need to ensure efficient proper ordering and enforcement of memory operations to maintain persistent state, as traditional methods like Data Synchronization Barriers (DSBs) limit flexibility and efficiency in instruction execution.
Innovation Solution
The introduction of explicit dependency keys (EDKs) and complementary parameters within the instruction set architecture (ISA) allows for the definition and enforcement of ordered constraints between instructions, eliminating the need for DSBs by explicitly defining dependencies between producer and consumer instructions, enabling more flexible and efficient execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Data Synchronization Barriers (DSBs) are used to ensure proper ordering of memory operations, then reliability of persistent state is improved, but device complexity and execution efficiency deteriorate
Solution Approach 1:
The patent segments the monolithic barrier synchronization mechanism into fine-grained per-instruction dependency specifications. Each instruction can independently specify its own ordering constraints with respect to other instructions, allowing the compiler or programmer to precisely define only the necessary ordering relationships rather than using broad barriers that constrain all subsequent instructions.
Solution Approach 2:
The patent introduces dynamic dependency specification where instructions can adaptively indicate their ordering requirements based on runtime conditions. The dependency metadata allows the execution engine to dynamically determine instruction ordering without static barrier constraints, enabling flexible reordering when dependencies are not violated.
2Reliability
If Data Synchronization Barriers (DSBs) are inserted to enforce memory operation ordering, then reliability of persistent state is improved, but productivity and execution speed deteriorate
Solution Approach 1:
The patent applies partial action by specifying ordering constraints only where necessary for correctness, rather than inserting barriers that constrain all memory operations. The dependency metadata allows selective enforcement of ordering only for instruction pairs that have actual dependency relationships, leaving other instructions free to execute in parallel or reordered fashion.
Solution Approach 2:
The patent changes the parameter of instruction ordering from a static barrier-based model to a dynamic dependency-based model. Instructions include metadata parameters that specify their ordering constraints, allowing the execution engine to adjust scheduling decisions based on actual dependency relationships rather than conservative barrier-imposed constraints.
3Reliability
If traditional barrier mechanisms are used for NVMM operations, then persistent state consistency is maintained, but adaptability and flexibility in instruction execution deteriorate
Solution Approach 1:
The patent introduces dynamic dependency specification where instructions can adaptively indicate their ordering requirements based on runtime conditions. The dependency metadata allows the execution engine to dynamically determine instruction ordering without static barrier constraints, enabling flexible reordering when dependencies are not violated.
Solution Approach 2:
The patent creates a universal dependency specification mechanism that works across all types of memory operations and instruction pairs, replacing the specialized barrier instruction. This multi-functional approach allows the same dependency metadata mechanism to handle various ordering scenarios (store-store, load-store, store-load) without requiring different synchronization primitives.
Data Source
AI summary
In a particular implementation, a method includes: receiving, at a computing device, first and second instructions of a plurality of instructions obtained from a memory, where the first instruction corresponds to a preceding instruction of a second instruction, and where the second instruction corresponds to a succeeding instruction of the first instruction; determining a dependency of the first and second instructions; sending the first and second instructions to an issue queue of the computing device; executing, at the computing device, the first and second instructions; and completing, at the computing device, the first and second instructions.