Exposing Internal Nodes in IC Design Verification
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Solution Overview
Problem
Current integrated circuit design verification processes are inefficient due to the manual and time-consuming process of accessing internal nodes within the RTL data structure, leading to synchronization issues between design and simulation processes.
Innovation Solution
The implementation of a control interface that receives parameters to expose internal inputs and outputs of module descriptions to simulators, allowing for signal forcing and monitoring, and generating annotations or configuration files to facilitate access to these nodes within the RTL data structure, enabling efficient testing and keeping design and simulation processes in sync.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual processes are used to access internal nodes in RTL data structure, then verification can be performed, but the process is time-consuming and inefficient
Solution Approach 1:
The patent introduces an intermediary layer (testbench code with force statements and node exposure mechanisms) that mediates between the simulator and the RTL data structure. This intermediary automatically handles the complex task of accessing internal nodes, transforming manual verification processes into automated operations that are both efficient and maintain synchronization between design and simulation.
2Reliability
If internal nodes are accessed manually, then verification testing can occur, but synchronization issues arise between design and simulation processes
Solution Approach 1:
The patent implements feedback mechanisms where the testbench code continuously monitors and adjusts its access to internal nodes based on the current state of the RTL data structure. This feedback loop ensures that the simulation process remains synchronized with the design, automatically detecting and correcting any desynchronization without manual intervention.
Solution Approach 2:
The system enables self-service by allowing the testbench to automatically expose and access internal nodes through programmed force statements and node exposure logic. The verification process serves itself by maintaining synchronization through automated mechanisms, eliminating the need for manual coordination between design and simulation teams.
3Productivity
If manual editing is used to access RTL nodes, then verification can proceed, but the process requires significant manual effort
Solution Approach 1:
The patent applies preliminary action by pre-programming the testbench with force statements and node exposure logic before simulation begins. This preliminary configuration automatically handles the complexity of accessing internal nodes during simulation, transforming a complex manual process into a straightforward automated execution that increases verification throughput without requiring manual editing during the simulation phase.
Data Source
AI summary
An integrated circuit design may be generated for an integrated circuit. The integrated circuit design may include an instance of a module description that describes a functional operation of a module. The instance may include an input that is internal to the integrated circuit design. The integrated circuit design may be encoded in an intermediate representation (IR) data structure. A parameter may be received indicating that the input should be exposed to a simulator. The IR data structure may be compiled to produce a register-transfer level (RTL) data structure. The RTL data structure may encode a logic description associated with the instance. The parameter may be used to permit a simulator to access a node in the RTL data structure that is associated with the input.