Exposed Die Clip Bond Power Package Thermal Management
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Solution Overview
Problem
The challenge in semiconductor packaging is to reduce the size of components while enhancing power-handling capabilities and thermal performance, particularly in reducing the drain/source electrical resistance (RDSon) to minimize electrical power loss, which is difficult with conventional packaging methods.
Innovation Solution
The solution involves exposing the die backside with a solderable coating and using a clip bond process to attach leads in direct die contact, minimizing thermal resistance between the die junction and the printed circuit board, and optionally adding multiple wire bonds for signal pathways, while encapsulating the package in a molding compound to maintain the solderable conductive surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional packaging methods are used, then the device structure is simple and easy to manufacture, but the thermal performance is poor and RDSon is high
Solution Approach 1:
The die backside is extracted and exposed externally through the package structure, allowing direct thermal contact with the printed circuit board. This extraction of the die backside from the traditional fully encapsulated structure enables minimal thermal resistance path while maintaining manageable package complexity through strategic exposure rather than full encapsulation.
Solution Approach 2:
The package structure transitions from a conventional top-down thermal path to a dual-path architecture by exposing the die backside. This dimensional change creates a vertical thermal pathway through the PCB while maintaining horizontal electrical connections, effectively utilizing three-dimensional space to reduce thermal resistance without significantly increasing package footprint.
2Area of stationary object
If the size of components is reduced, then the printed circuit substrate space is reduced, but the power-handling capabilities and thermal performance deteriorate
Solution Approach 1:
The package utilizes vertical dimension by exposing the die backside to contact with the PCB, creating a through-substrate thermal pathway. This three-dimensional thermal management approach allows compact horizontal footprint while maintaining effective thermal dissipation through the vertical path, preventing thermal performance deterioration despite reduced component size.
Solution Approach 2:
The package structure applies different qualities to different regions: the die backside area is exposed for direct thermal contact with the PCB, while other areas are encapsulated for protection. This localized exposure strategy optimizes thermal performance in the critical heat dissipation region without requiring the entire package to be oversized, thus maintaining compact substrate space utilization.
3Adaptability or versatility
If the number of electronic devices per wafer area is increased, then the device functionality is enhanced, but the manufacturing difficulty increases
Solution Approach 1:
The exposed die backside structure serves multiple functions simultaneously: it provides a thermal pathway to the PCB, creates an electrical connection surface, and enables direct mounting of the device array. This multi-functionality allows the same structural feature to support enhanced device functionality through dense integration while simplifying the manufacturing process by eliminating separate thermal management components.
Solution Approach 2:
The package merges the thermal management function, electrical connection function, and mechanical mounting function into a single integrated structure where the die backside exposure serves all three purposes. This consolidation reduces manufacturing complexity despite increased device density by eliminating the need for separate thermal vias, additional bonding layers, and complex assembly steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves minimal RDSon, enhancing thermal performance and power-handling capabilities by reducing electrical resistance and allowing for efficient heat dissipation, thereby improving the overall performance of semiconductor power packages.
Implementation Method 1
minimal thermal resistance is achieved between the die junction and the printed circuit board to which the packaged device is attached
Implementation Method 2
A solder paste is dispensed onto the bond pads on the plurality active device die. A lead frame is attached to the temporary carrier, the lead frame having an array of device positions which correspond to the predetermined positions of the plurality of active device die, wherein upper lead frame portions contact the solder paste present on the bond pads and lower lead frame portions contact the temporary carrier. There is a reflowing of the solder so that a connection is made between the upper lead frame portions and the bond pads of the plurality of active device die.
Data Source
AI summary
In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.