Exposed Die Package Direct Soldering Thermal Management
Solution Overview
Problem
Conventional semiconductor packages face challenges with heat dissipation due to high thermal resistance resulting from multiple interfaces in the cooling path, leading to increased junction temperatures and manufacturing costs.
Innovation Solution
A packaged semiconductor device with a semiconductor die having a planar backside metal layer directly attached to the bottomside, allowing for direct soldering to a printed circuit board (PCB) without thermal grease or heat sinks, reducing thermal resistance and assembly complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional power packages (exposed heat slug or exposed silicon) are used, then cooling is provided, but thermal resistance is high due to multiple interfaces in the cooling path
Solution Approach 1:
The patent extracts and eliminates the intermediate thermal interfaces (thermal grease layer and heat sink) from the cooling path. By exposing the backside metal layer of the semiconductor die and making it substantially planar, the invention creates a direct thermal path from the die to the PCB workpiece, removing the thermal resistance introduced by multiple interfaces.
Solution Approach 2:
The patent merges the semiconductor die backside metal layer directly with the PCB workpiece through soldering, eliminating the separation created by conventional heat sinks and thermal grease. This merging creates a unified thermal path that reduces thermal resistance and improves heat dissipation efficiency.
2Loss of energy
If multiple interfaces (substrate, die attach material, heat slug, solder) are included in the cooling path, then cooling is achieved, but thermal resistance increases
Solution Approach 1:
The invention extracts and removes the unnecessary intermediate layers (thermal grease, heat sink mounting structures) from the cooling path. By exposing the backside metal layer and making it planar, the patent reduces the number of interfaces from multiple layers to a direct solder joint between the die backside and PCB workpiece.
3Temperature
If conventional assembly methods with thermal grease and heat sinks are used, then cooling is provided, but assembly cost increases
Solution Approach 1:
The patent extracts and eliminates expensive components (heat sinks, thermal grease materials, complex mounting structures) from the assembly. By creating a planar backside metal layer that can be directly soldered to the PCB, the invention simplifies the manufacturing process and reduces material costs while maintaining effective heat dissipation.
4Loss of energy
If intermediate cooling components (thermal grease, heat sink) are used, then cooling is achieved, but board space increases
Solution Approach 1:
The invention removes the space-consuming intermediate cooling components (heat sinks, thermal grease layers, mounting structures) from the PCB assembly. By enabling direct soldering of the exposed backside metal layer to the PCB workpiece, the patent eliminates the need for additional cooling components that would occupy valuable board space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances heat dissipation, reduces assembly costs, and minimizes board space requirements by eliminating intermediate interfaces, thereby improving the thermal performance and manufacturing efficiency of semiconductor devices.
Implementation Method 1
improved heat dissipation to the workpiece (e.g., PCB) due to a reduction in interfaces in the thermal cooling path
Implementation Method 2
Direct solder connections are provided from the backside metal layer and the bonding portions of the leads to the surface pads on the PCB
Data Source
AI summary
A method of forming an electronic assembly includes attaching a backside metal layer the bottomside of a semiconductor die. An area of the backside metal layer matches an area of the bottomside of the die. A die pad and leads are encapsulated within the molding material. The leads include an exposed portion that includes a bonding portion. A gap exposes the backside metal layer along a bottom surface of the package. Bond wires couple the pads on the topside of the die to the leads and the bonding portions. Packaged semiconductor device is soldered to a printed circuit board (PCB). The backside metal layer and the bonding portions of the leads are soldered substrate pads on said PCB.