Exposed Semiconductor Package Thermal Dissipation
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Solution Overview
Problem
Semiconductor packages face challenges in effectively dissipating generated heat, which affects their performance and reliability as electronic devices become faster, smaller, and more powerful.
Innovation Solution
A semiconductor package design that includes a substrate with conductive patterns, semiconductor chips connected by a connecting member, and a sealing member that exposes the lower surface of the substrate and upper surface of the connecting member to facilitate heat dissipation, along with optional features like a heat sink and metal slug for enhanced thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the semiconductor package uses a conventional sealed structure, then the package is well-protected, but heat dissipation is insufficient
Solution Approach 1:
The patent extracts the sealing function from the entire package structure by introducing a dedicated sealing member that selectively seals only the necessary regions while leaving heat-dissipating surfaces exposed. This allows the package to maintain protection where needed while enabling heat dissipation through exposed conductive patterns and substrate surfaces.
Solution Approach 2:
The sealing member is designed to provide localized sealing rather than complete enclosure. It seals the peripheral regions to protect internal components while leaving the lower substrate surface and upper connecting member surfaces exposed for heat dissipation, creating different functional zones within the same package structure.
2Volume of moving object
If the package size is reduced to meet miniaturization requirements, then the device becomes more compact, but heat dissipation capability deteriorates
Solution Approach 1:
The patent transitions from conventional planar heat dissipation to three-dimensional multi-surface heat dissipation. By exposing both the lower substrate surface and upper connecting member surfaces, heat can dissipate in multiple spatial dimensions simultaneously, maintaining effective heat dissipation capability despite reduced package volume.
Solution Approach 2:
The conductive patterns serve multiple functions: they provide electrical connection between components and simultaneously act as heat dissipation paths. The exposed surfaces of both substrate and connecting members serve dual purposes of structural support and thermal management, maximizing functionality within limited space.
3Temperature
If conductive patterns are spaced apart to enable heat dissipation, then thermal performance improves, but electrical connection reliability may be affected
Solution Approach 1:
The connecting member acts as an intermediary that bridges the spaced-apart conductive patterns. It provides both electrical connection between the patterns and additional heat dissipation surface area, resolving the conflict between electrical connectivity and thermal performance by introducing a mediating component that fulfills both functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for effective heat dissipation through both the upper and lower surfaces of the package, improving the stability and performance of semiconductor devices while reducing thermal and electrical resistance.
Implementation Method 1
a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip to each other
Implementation Method 2
a heat sink contacting the lower surface of the substrate exposed to the outside by the sealing member
Data Source
AI summary
A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.