Exposed Semiconductor Connection Terminal for Stacked Device Reliability
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Solution Overview
Problem
Conventional semiconductor device stacking configurations face challenges in achieving higher density packaging due to misalignment of connection terminals and resin layers, leading to gaps that prevent connection and potential damage to semiconductor chips during resin-sealing processes.
Innovation Solution
A semiconductor device configuration where the external connection terminal is exposed from the resin layer, forming a single plane with it, allowing for reliable connection even with low-height terminals without requiring reduced resin layer thickness, and a manufacturing method that includes deforming the terminal and sealing it within the resin layer to prevent chip damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of external connection terminal is reduced to achieve higher density packaging, then the packaging density is improved, but the connection reliability deteriorates due to gap formation with resin layer
Solution Approach 1:
The patent applies preliminary action by forming the external connection terminal before the resin sealing process, and intentionally designing it to protrude from the resin surface. This preliminary positioning ensures that the terminal is already in the correct position and height relative to the resin layer, eliminating the need for post-sealing adjustments and preventing gap formation during stacking operations.
Solution Approach 2:
The patent changes the parameter of terminal height relative to the resin surface, specifically designing the terminal to protrude from the resin surface by a controlled amount. This parameter change transforms the terminal from being embedded or flush with the resin surface to protruding, which ensures reliable electrical connection during stacking while maintaining compact packaging dimensions.
2Length of stationary object
If the resin layer thickness is reduced to accommodate low-height terminals, then the device thickness is reduced, but the manufacturing complexity increases due to need for specialized thinning technologies
Solution Approach 1:
The patent inverts the conventional approach by not reducing the resin layer thickness to accommodate terminals, but rather allowing the terminal to protrude from the resin surface. This inversion eliminates the need for complex terminal embedding techniques and specialized thinning technologies, simplifying the manufacturing process while achieving compact device thickness.
3Reliability
If the external connection terminal is exposed from the resin layer, then the connection reliability is improved, but the manufacturing precision requirement increases to ensure proper alignment
Solution Approach 1:
The patent merges the terminal formation process with the resin sealing process, where the terminal is formed to protrude from the resin surface as an integrated feature rather than a separate post-processing step. This merging of processes ensures that the terminal and resin layer are inherently aligned, reducing the need for separate alignment operations and minimizing the precision requirements for each individual step.
Data Source
AI summary
A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal electrically connected to the base substrate via a wiring layer. The external connection terminal is in the same plane as the surface of the resin layer, and is exposed from the resin layer. With this configuration, it is possible to provide a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.