Extendable Hardware Queue Structure with Internal and External Memory
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Solution Overview
Problem
Integrated circuit devices face performance issues due to the use of external queue memory, which increases latency and costs associated with onboard queue memory sizing, as existing hardware queues struggle to manage transitions between internal and external memory efficiently.
Innovation Solution
A method and apparatus for managing a hardware queue with internal and external queue memories by monitoring occupancy and controlling pointers to seamlessly transition data between the two, using internal and external tail and head pointers, along with wrap pointers, to maintain continuous operation and balance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external queue memory is used to extend onboard queue capacity, then queue capacity is increased, but latency increases and performance deteriorates
Solution Approach 1:
The queue memory is segmented into two distinct parts: onboard queue memory (fast, low-latency) and external queue memory (slow, high-latency). The system divides the queue operation into segments that operate independently - critical operations remain on onboard memory while non-critical operations use external memory, allowing the system to achieve both high capacity and low latency for time-sensitive operations.
Solution Approach 2:
Different quality levels are applied to different parts of the queue system. The onboard queue memory provides high-speed access for critical data elements, while the external queue memory provides high-capacity storage for less time-sensitive data. This local differentiation allows the system to optimize for both speed and capacity in appropriate contexts.
2Loss of time
If onboard queue memory size is increased to avoid using external memory, then latency is reduced, but cost increases
Solution Approach 1:
Instead of providing full queue capacity through expensive onboard memory, the system provides partial capacity through onboard memory and supplements it with external memory when needed. This partial action approach achieves acceptable performance for critical operations while using cost-effective external storage for overflow capacity.
Solution Approach 2:
The external queue memory serves as a disposable or temporary extension for queue operations. When the onboard queue is full, data is offloaded to the cheaper external memory, which can be accessed when needed but is not continuously occupied. This allows the system to use inexpensive storage for capacity while reserving expensive onboard memory for active operations.
3Productivity
If seamless transition between internal and external memory is implemented, then system performance is enhanced, but device complexity increases
Solution Approach 1:
The tail pointer and head pointer act as intermediaries that automatically manage transitions between onboard and external queue memories. These pointers monitor queue occupancy and trigger data movement between memory types without requiring complex control logic or intervention, simplifying the transition management while maintaining seamless operation.
Solution Approach 2:
The queue system manages its own transitions between internal and external memory through automatic monitoring of occupancy levels and self-triggered data movement. The tail pointer detects when onboard memory is full and automatically initiates transfer to external memory, while the head pointer similarly manages retrieval operations, eliminating the need for external control mechanisms.
Data Source
AI summary
A hardware queue for an integrated circuit device includes an internal queue memory and at least one external queue memory. The internal queue memory and the external queue memory are operated as a continuous hardware queue memory by monitoring occupancy of the internal queue memory and, based on that occupancy, controlling an internal tail pointer indicating a next write point for inserting new data into the internal queue memory, an internal head pointer indicating a next read point for extracting data from the internal queue memory based on order of insertion, at least one external tail pointer indicating a next write point for inserting new data into the external queue memory, at least one external head pointer indicating a next read point for extracting data from the external queue memory based on order of insertion, and wrap pointers indicating transitions between the internal queue memory and the external queue memory.