Extendable Parity Matrices for Adaptive ECC Decoding
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Solution Overview
Problem
Current data storage devices face challenges in supporting variable code rates and parity bit configurations, limiting their ability to adapt to different error correction needs across various regions on the storage medium.
Innovation Solution
The implementation of extendable parity code matrices, which include a primary parity matrix and its incremental extensions, allows for multiple code rates and numbers of parity bits, enabling flexible error correction operations by selecting the appropriate parity matrix based on the desired code rate and error rate of the data unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed parity matrix is used for error correction, then the device complexity is reduced, but the adaptability to different code rates and error correction needs is limited
Solution Approach 1:
The patent implements a dynamic parity matrix selection mechanism where the system can switch between a primary parity matrix and multiple extended parity matrices based on the detected bit error rate. This allows the error correction code rate to adapt dynamically to different channel conditions without requiring multiple fixed configurations, thereby improving adaptability while maintaining manageable device complexity through a systematic extension approach.
Solution Approach 2:
The system changes the parameter of the parity matrix by extending the primary matrix with additional rows to create extended parity matrices with different code rates. This parameter change approach allows the system to adjust the number of parity bits and code rate according to the actual error conditions, achieving versatility without requiring completely separate matrix configurations for each code rate.
2Reliability
If multiple parity matrices are configured for different code rates, then the adaptability to varying error rates is improved, but the device complexity increases
Solution Approach 1:
The patent segments the parity matrix into a primary matrix and multiple extended matrices, where each extended matrix is created by adding specific rows to the primary matrix. This segmentation allows the system to handle different error correction needs through modular matrix extensions rather than requiring completely separate matrices, thereby improving reliability while controlling the growth of device complexity through a structured segmentation approach.
Solution Approach 2:
The extended parity matrices are nested based on the primary parity matrix, where each extended matrix contains the primary matrix as a subset with additional rows appended. This nesting structure allows the system to build upon a single primary matrix configuration to achieve multiple code rates, improving error correction capability across different conditions while avoiding the complexity of storing completely independent matrices for each code rate.
3Reliability
If the number of parity bits is increased for higher code rates, then the error correction capability is improved, but the storage efficiency and productivity are reduced
Solution Approach 1:
The system dynamically adjusts the number of parity bits by selecting between the primary parity matrix and extended parity matrices based on the actual bit error rate detected during read operations. This dynamic adjustment ensures that additional parity bits are only used when error correction is actually needed, thereby improving reliability when required while maintaining data storage efficiency under normal operating conditions.
Solution Approach 2:
The system changes the parameter of the code rate by selecting different parity matrix configurations based on channel conditions. When the bit error rate is low, the system uses the primary matrix with fewer parity bits for optimal storage efficiency. When the bit error rate increases, the system extends to matrices with more parity bits to improve error correction capability, thus adapting the parameter to balance reliability and productivity based on actual needs.
Data Source
AI summary
Example channel circuits, data storage devices, and methods for using an extendable parity code matrix are described. A data unit may be read from a storage medium. Multiple sets of parity bits may be available for the data unit, each set of parity bits having a different number of parity bits corresponding to different parity matrices, including a primary parity matrix and at least one extended parity matrix. The extended parity matrix includes the primary parity matrix and additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data unit based on the data unit from the read signal.