Extendable Squarer Circuit for Digital Signal Processing
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Solution Overview
Problem
Existing squarer circuits in VLSI and communication systems require hundreds of thousands of multipliers due to complex operating systems, leading to increased costs and conflicting with the trend of circuit integration.
Innovation Solution
An extendable squarer with a bit expanding circuit and operating units that generate bit expanding data and operators to perform square operations efficiently, reducing the size of the circuit by using a binary weight-based method to calculate square values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional multipliers are used to execute square operations, then the square operation can be performed, but the circuit size increases and costs increase due to requiring hundreds of thousands of multipliers
Solution Approach 1:
The patent segments the square operation into multiple partial product terms that can be processed in parallel. By dividing the n-bit data into smaller segments and computing partial products separately, the circuit avoids using hundreds of thousands of multipliers while maintaining computational accuracy. Each segment processes a portion of the square operation, and the results are summed to produce the final square value.
Solution Approach 2:
The patent transforms the traditional multiplication-based square operation into a dimensionally different approach by using a segmented summation method. Instead of relying on multiple multiplier units operating in the traditional dimension, the invention reorganizes the computation into partial product terms that are summed across different dimensional segments, reducing the overall circuit footprint.
2Productivity
If traditional square operation circuits are used, then square operations can be executed, but the circuit size becomes large conflicting with the trend of circuit integration
Solution Approach 1:
The circuit is segmented into multiple operating units that each handle specific partial product terms. This segmentation allows for more compact arrangement of circuit elements, increasing integration density while reducing the total circuit area. Each operating unit is optimized to process a specific segment of the square operation efficiently.
Solution Approach 2:
The patent merges multiple computation functions into a unified segmented architecture. By combining the generation of partial product terms with the summation process in an integrated manner, the circuit achieves higher integration density. The operating units are designed to perform multiple functions within a compact structure, reducing the overall circuit area.
Data Source
AI summary
An extendable squarer for processing digital signals, suitable for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n−1 bit expanding output terminals for outputting a plurality of bit expanding data. The operation units receive a plurality of bit codes of the n-bit data corresponding thereto according to the binary weight. In addition, except for bit code of the most-significant bit, the other operation units receive the corresponding bit expanding data output by the bit expanding circuit respectively. The present invention generates the square operation value of the n-bit data based on the corresponding bit expanding data and bit codes.