Extended AES-XTS Memory Encryption Tweak for Replay Attack Mitigation

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Solution Overview

Problem

Existing methods for protecting secure software applications in external memory from malicious modifications, such as replay attacks, are inadequate as they either rely on expensive large volatile memory integration in the CPU or require additional memory for authentication tags, and current encryption techniques like XTS-AES do not effectively prevent attackers from inducing random changes or replaying encrypted memory images.

Innovation Solution

An enhanced mode of operation for block ciphers, specifically extending the XTS-AES mode by incorporating a timestamp and additional labels into the tweak value, which binds encryption to both physical memory addresses and temporal information, effectively preventing replay attacks by ensuring that decrypted data from a different time or context is unpredictable and uncontrollable.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If large volatile memory is integrated in the CPU package to protect secure software applications, then security protection is improved, but cost increases

Engineering Contradiction:
Improvesecurity protectionVSAvoidcost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent combines encryption and authentication functions into a single memory encryption system using XTS-AES mode with extended tweak values. This integration eliminates the need for separate authentication tags in additional memory, reducing overall memory requirements while maintaining security protection.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extends the tweak value parameters in the XTS-AES encryption mode to include additional information beyond standard address bits. This parameter extension enables the system to provide both encryption and authentication functionality using the same memory space, avoiding the need for expensive memory integration.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If additional memory is allocated for authentication tags to prevent replay attacks, then security protection is improved, but memory usage increases

Engineering Contradiction:
Improveprotection against replay attacksVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent merges authentication data into the encryption process itself by using extended tweak values in XTS-AES mode. The authentication information is embedded within the existing memory structure rather than requiring separate authentication tags in additional memory space.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The extended tweak value mechanism serves multiple functions simultaneously: it provides standard encryption functionality while also incorporating authentication capabilities. This multi-functionality eliminates the need for dedicated authentication memory while maintaining protection against replay attacks.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If standard XTS-AES encryption is used without extended tweak values, then device complexity is reduced, but protection against replay attacks deteriorates

Engineering Contradiction:
Improveencryption implementationVSAvoidprotection against replay attacks
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent extends the tweak value parameters in XTS-AES to include additional fields such as address bits and authentication data. This parameter extension enables replay attack protection while maintaining compatibility with the standard XTS-AES encryption framework, avoiding significant increases in device complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2619705B1A tweakable encryption mode for memory encryption with protection against replay attacks
Publication Date: 2017.12.27 INTEL CORP
  • EP2619705B1 patent drawingFigure 1
  • EP2619705B1 patent drawingFigure 2A~2B
  • EP2619705B1 patent drawingFigure 3

AI summary

A method and apparatus for protecting against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a "time stamp" indicator. An incrementing mechanism using the "time stamp" indicator generates a tweak which separates different contexts over different times such that the effect of "Type 2 replay attacks" is mitigated.