Extended Bitline Air Gap Height for 3D NAND Capacitance
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Solution Overview
Problem
In 3D-NAND memory structures, the increasing number of tiers and word lines leads to a higher number of contacts, requiring more routing paths, which complicates the connection to CMOS devices and affects bitline performance due to limited bitline airgap height.
Innovation Solution
An extended bitline air gap structure is formed by depositing a dielectric layer on top of the bitline layer, followed by a subtractive bitline etch and an air gap dielectric deposition that extends beyond the bitline contacts, improving bitline capacitance and RC time constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of tiers and word lines is increased to achieve higher 3D NAND density, then storage capacity is improved, but the number of contacts increases requiring more routing paths which complicates the connection to CMOS devices and degrades bitline performance
Solution Approach 1:
The patent extends the air gap structure vertically beyond the bitline contact height to create additional capacitance. By adding height in the vertical dimension rather than expanding laterally, the design improves bitline performance without increasing planar footprint or routing complexity, thus resolving the contradiction between storage density and device complexity
Solution Approach 2:
The patent modifies the air gap height parameter to extend beyond the bitline contact height. This parameter change increases bitline capacitance and improves RC time constant without requiring additional routing paths or contacts, thereby maintaining routing simplicity while achieving better electrical performance to support higher density
2Speed
If the air gap height is extended beyond bitline contacts to improve bitline capacitance, then bitline RC time constant is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent performs preliminary actions by first forming a dielectric layer over the bitline contacts before completing the air gap formation. This preliminary dielectric layer serves as a template that defines the extended air gap height, allowing the air gap to be formed in a controlled manner that achieves the desired capacitance improvement without requiring complex post-processing steps
Solution Approach 2:
The air gap formation process is segmented into multiple steps: first forming a dielectric layer over the contacts, then selectively removing portions to create the extended air gap structure. This segmentation allows precise control over the air gap height and shape, achieving improved bitline performance while maintaining manufacturing feasibility through standardized lithography and etching processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances bitline capacitance, leading to improved Input/Output speed and reduced power consumption, and decreases 3D NAND program latency by extending the air gap height beyond the bitline contacts.
Implementation Method 1
an air gap dielectric layer is deposited over the plurality of bitline contacts
Data Source
AI summary
Systems, apparatuses, and methods may provide for technology for forming extended air gaps for bitline contacts. For example, such technology patterns and etches a dielectric layer and a bitline layer to create bitline contacts in a memory die. An air gap dielectric layer is deposited to form an air gap between adjacent bitline contacts, and wherein the air gap has a height dimension that extends past a height dimension of the bitline contacts.