Extended BTB Entries for Single-Cycle Branch Prediction
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Solution Overview
Problem
Conventional branch prediction mechanisms in microprocessors face inefficiencies due to additional processor cycles required for accessing branch target buffer (BTB) when the predicted target address of a branch instruction is in a different memory block, leading to reduced performance and increased power consumption.
Innovation Solution
Implementing extended branch target buffer (BTB) entries that store both trunk and leaf branch metadata within a single entry, allowing for efficient retrieval and prediction of branch instructions within the same processor cycle, even when the target address is in a different memory block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the processor performs an additional access to the BTB to retrieve metadata for branch instructions in a different aligned memory block, then the branch prediction accuracy is improved, but the processor cycle time increases and performance deteriorates
Solution Approach 1:
The patent merges trunk branch metadata and leaf branch metadata into a single extended BTB entry. When a trunk branch instruction is predicted to be taken, the processor can retrieve both the trunk branch target address and the leaf branch metadata (including subsequent branch instructions at the target address) in a single BTB access, eliminating the need for a second access and reducing processor cycle time while maintaining prediction accuracy
Solution Approach 2:
The patent performs preliminary action by pre-fetching and storing metadata for leaf branch instructions (branches at target addresses) into the extended BTB entry during the initial BTB access. This allows the processor to have branch prediction information for subsequent branches already available before execution reaches those instructions, avoiding latency when those branches are encountered
2Loss of time
If the fetch bundle is terminated at the predicted-taken branch instruction to avoid additional BTB accesses, then the processor cycle time is reduced, but the front-end instruction pipeline throughput is limited
Solution Approach 1:
By combining trunk and leaf branch metadata in a single extended BTB entry, the processor can generate predictions for multiple branch instructions (both the trunk branch and leaf branches at the target address) within the same processor cycle, allowing the fetch bundle to extend beyond the predicted-taken branch instruction without requiring additional BTB access cycles
Solution Approach 2:
The extended BTB entry enables continuous useful action by allowing the branch predictor circuit to generate predictions for multiple consecutive branch instructions in one processor cycle. This maintains high instruction pipeline throughput by keeping the fetch stage actively producing fetch bundles for multiple instructions without idle cycles caused by repeated BTB accesses
Data Source
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AI summary
Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata is disclosed herein. In one aspect, a processor comprises a BTB circuit comprising a BTB comprising a plurality of extended BTB entries. The BTB circuit is configured to store trunk branch metadata for a first branch instruction in an extended BTB entry of the plurality of extended BTB entries, wherein the extended BTB entry corresponds to a first aligned memory block containing an address of the first branch instruction. The BTB circuit is also configured to store leaf branch metadata for a second branch instruction in the extended BTB entry in association with the trunk branch metadata, wherein an address of the second branch instruction is subsequent to a target address of the first branch instruction within a second aligned memory block.