Extended Charge Trapping Layer Memory Array Design
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Solution Overview
Problem
Conventional charge trapping memory cells face issues where charges get trapped in spacer material during erasure, leading to source/drain region depletion, increased resistance, and voltage drops across the memory array.
Innovation Solution
A memory array design with a wider charge trapping layer extending beyond the gate region to capture and remove charges, reducing depletion and resistance by facilitating efficient charge trapping and erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge trapping memory cells use conventional spacer material separation, then memory cell structure is maintained, but charges become trapped in spacer material during erasure causing source/drain region depletion and increased resistance
Solution Approach 1:
The charge trapping layer is segmented into two distinct regions: a first charge trapping region directly over the source/drain regions and a second charge trapping region over the channel region, separated by the gate electrode. This segmentation allows charges to be trapped in specific regions without depleting the source/drain areas, resolving the contradiction between effective charge trapping and maintaining source/drain region integrity.
Solution Approach 2:
The gate electrode acts as an intermediary element positioned between the first and second charge trapping regions. It facilitates the separation of charge trapping functions while preventing charge accumulation in the spacer material, thereby eliminating the harmful depletion effect in source/drain regions during erasure operations.
2Productivity
If charges are trapped in spacer material during erasure, then memory cell erasure is achieved, but resistance increases and voltage drops increase across the memory array
Solution Approach 1:
Different regions of the charge trapping layer are assigned different functions: the first charge trapping region handles charge storage near source/drain areas while the second charge trapping region handles channel region charges. This local differentiation ensures that erasure operations do not trap charges in spacer material, maintaining both erasure efficiency and voltage stability across the memory array.
3Reliability
If charge trapping layer is extended beyond gate region, then charge capturing and removing is facilitated reducing depletion and resistance, but device complexity increases
Solution Approach 1:
The extended charge trapping layer structure serves multiple functions simultaneously: it traps charges during programming, removes charges during erasure, and prevents charge accumulation in spacer regions. This multi-functionality is achieved through the continuous charge trapping layer that extends beyond the gate region, resolving the contradiction between improved charge management and device complexity by making the existing structure perform additional critical functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces depletion in source/drain regions, lowers contact resistance, and minimizes voltage drops across the memory array, ensuring accurate sensing during read operations and enabling smaller memory device sizes.
Implementation Method 1
a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges
Data Source
AI summary
A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.