Extended DPDCH Secondary Despread for Low Latency
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Solution Overview
Problem
Conventional DPDCH data processing methods incur significant logic processing delay, making them unsuitable for supporting high-demand services like HSDPA MIMO and HSPA+ due to the need for complete frame reception before secondary despreading can occur.
Innovation Solution
The method involves sending a request for secondary despread after completing softer merging for one timeslot of extended DPDCH data, determining channels by priority, and performing secondary despread and framing on the highest-priority channel, allowing for reduced processing delay and supporting higher logic processing requirements without affecting normal DPDCH data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional DPDCH data processing methods are used where secondary despreading is performed only after complete frame reception, then processing completeness is ensured, but logic processing delay becomes too great to support high-demand services like HSDPA MIMO and HSPA+
Solution Approach 1:
The patent segments the DPDCH data processing into two distinct modes: normal processing mode (for complete frames) and extended processing mode (for partial timeslot data). This segmentation allows the system to apply different processing strategies based on service requirements, enabling low-latency processing for time-critical services while maintaining complete processing for traditional services.
Solution Approach 2:
The patent introduces dynamic mode switching between normal and extended processing modes based on service type requirements. The system can dynamically select the appropriate processing mode: extended mode for HSDPA MIMO/HSPA+ services requiring low latency, and normal mode for services requiring complete frame processing. This dynamic adaptability resolves the contradiction by making processing delay adjustable rather than fixed.
2Productivity
If extended DPDCH data processing is implemented to reduce time delay by processing at timeslot frequency, then support for high-demand services is enabled, but system complexity increases due to multiple processing modes
Solution Approach 1:
The patent performs preliminary actions by pre-configuring extended DPDCH parameters and establishing processing rules before actual data arrival. The system pre-defines the extended processing mode parameters, channel priority orders, and switching conditions, so that when extended DPDCH data arrives, the system can immediately switch to the appropriate mode without complex real-time decision-making, thereby reducing the perceived complexity.
Solution Approach 2:
The patent designs a universal processing framework that handles both normal and extended DPDCH modes through a single integrated system. The same processing unit can operate in either mode depending on configuration, and the system universally applies the same core processing algorithms (soft merging, secondary despreading, framing) across both modes, reducing overall system complexity despite supporting multiple processing scenarios.
Data Source
AI summary
A method and a device for processing data in a dedicated physical data channel, comprising, when data on which softer handover is performed is extended DPDCH data, sending, after completing the softer merging of the data for one timeslot, a request for secondary despread, where the request contains channel numbers; acquiring the request for secondary despread, determining channels according to the channel numbers contained in the request for secondary despread, determining a channel having the highest priority from the channels according to a predetermined channel priority order, and secondarily despreading, framing and outputting data of the channel having the highest priority. Due to the arrangement of the extended DPDCH, embodiments of this invention process the data carried by the extended DPDCH at the frequency of timeslots, and thus reduce the time delay of the second despreading and support services having higher requirements for logic processing delay without affecting the process for the existing normal DPDCH data.