Extended-Drain MOS Structure With Drain-Well Gap for Lower Capacitance
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Solution Overview
Problem
Extended-drain metal-oxide-semiconductor devices face increased output capacitance issues due to parasitic gate-drain and gate-source capacitances, which negatively impact switching performance as device size decreases.
Innovation Solution
A structure and method for forming an extended-drain metal-oxide-semiconductor device with a semiconductor substrate, body wells, source and drain regions, and a gate electrode, where the drain well is laterally spaced from the body wells, reducing parasitic capacitance by creating gaps that are fully overlapped by the gate electrodes, thereby minimizing output capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If device size is reduced, then integration density is improved, but output capacitance increases to unacceptable values
Solution Approach 1:
The drain structure is segmented into a first drain region and a second drain region that are laterally spaced apart and separated by a gap. This segmentation reduces the parasitic gate-drain capacitance by breaking up the continuous capacitive coupling between the gate and the drain, thereby reducing total output capacitance while maintaining compact device footprint
Solution Approach 2:
A gap is introduced as an intermediary space between the first drain region and the second drain region. This gap acts as a mediator that reduces the parasitic capacitance by increasing the physical separation between charged regions, thereby lowering the output capacitance without significantly increasing the overall device area
2Area of moving object
If drain well is positioned adjacent to body well, then device area is reduced, but parasitic capacitance increases
Solution Approach 1:
The drain structure is divided into spatially separated first and second drain regions with a gap between them. This segmentation allows the drain to maintain electrical functionality while reducing the parasitic capacitance generated by close proximity to the body well, as the gap interrupts the continuous capacitive coupling path
Solution Approach 2:
Different regions of the drain structure are given different spatial positions - the first drain region is positioned closer to the source while the second drain region is laterally spaced further away. This local quality differentiation optimizes the balance between maintaining electrical performance and reducing parasitic capacitance in specific areas
Data Source
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AI summary
A structure for an extended-drain metal-oxide-semiconductor device, the structure comprising: a semiconductor substrate; a body well in the semiconductor substrate; a source region in the body well; a drain well in the semiconductor substrate, the drain well including an edge adjacent to the body well, and the edge of the drain well having a spaced relationship with the body well; a drain region in the drain well; and a gate electrode laterally positioned between the source region and the drain region.