Extended Drain MOS Device for FDSOI Breakdown Voltage
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Solution Overview
Problem
Current fully depleted silicon on oxide (FDSOI) semiconductor devices lack high voltage capabilities due to inadequate breakdown voltage, which limits their application in power amplifier and power management, as they break down under increasing operating voltages, leading to issues like punch-through and gate oxide breakdown.
Innovation Solution
Implementing an extended drain architecture with a spacer layer to constrain epitaxial growth, ensuring the gate is closer to the source than the drain, and using a photoresist to protect the extended drain region during spacer deposition, thereby preventing unconstrained epitaxial growth and maintaining higher breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FDSOI devices are made with smaller process technologies to achieve higher performance and lower power, then circuit packing density increases, but breakdown voltage becomes inadequate for high voltage applications
Solution Approach 1:
The device is segmented into distinct regions with different functions: a first drain region with higher doping concentration for standard operation, and a second drain region with lower doping concentration specifically designed to enhance breakdown voltage. This segmentation allows the device to simultaneously achieve high performance at small nodes while providing adequate voltage breakdown protection for high voltage applications.
Solution Approach 2:
Different regions of the device are given different local properties: the first drain region has higher doping concentration (1E18 to 1E20 atoms/cm³) for optimal current flow, while the second drain region has lower doping concentration (1E16 to 1E18 atoms/cm³) specifically to increase breakdown voltage. This local differentiation resolves the contradiction by allowing each region to optimize for its specific function.
2Adaptability or versatility
If operating voltage is increased to enable power amplifier and power management applications, then device capability expands, but punch-through and avalanche breakdown occur
Solution Approach 1:
The second drain region with lower doping concentration is built in advance as a protective structure that prevents punch-through and avalanche breakdown before they can occur during operation. This region acts as a cushion that absorbs and dissipates high voltage stress, enabling the device to safely operate in power amplifier and power management applications without suffering from voltage breakdown.
3Speed
If gate is positioned closer to source to improve performance, then device speed increases, but breakdown voltage decreases
Solution Approach 1:
The drain structure is segmented into two regions with different doping concentrations. The first drain region allows the gate to be positioned closer to the source for high-speed operation, while the second drain region with lower doping concentration compensates for the reduced breakdown voltage by providing an extended depletion region that prevents punch-through.
Solution Approach 2:
The drain structure exhibits asymmetry in doping concentration distribution, with the first drain region having higher doping than the second drain region. This asymmetric design allows the gate to be optimized for speed while the lower-doped second region provides the necessary breakdown voltage protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The extended drain architecture with constrained epitaxial growth enhances the breakdown voltage, making FDSOI devices suitable for high voltage applications while maintaining performance and preventing performance degradation.
Implementation Method 1
constrain epitaxial growth
Implementation Method 2
using a photoresist to protect the extended drain region during spacer deposition
Data Source
AI summary
A field effect transistor (FET) with raised source/drain region of the device so as to constrain the epitaxial growth of the drain region. The arrangement of the spacer layer is created by depositing a photoresist over the extended drain layer during a photolithographic process.