Extended-Drain MOS Transistor With Double Back Gate
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Solution Overview
Problem
Extended-drain MOS transistors in thin semiconductor layers on insulating substrates face a trade-off between high breakdown voltage and low conduction resistance, with conventional designs either sacrificing breakdown voltage for higher resistance or vice versa.
Innovation Solution
The implementation of a silicon-on-insulator type N-channel extended-drain transistor with a P-type source region and an N-type drain region, where the biasing of these regions is optimized to maintain a reverse-biased junction, and the use of a double back gate configuration to independently control the electrostatic behavior and resistivity of the drain extension region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an extended-drain MOS transistor is formed in a thin silicon layer on a buried oxide layer, then the breakdown voltage is increased, but the conduction resistance increases due to current flow in the medium-doped drift zone
Solution Approach 1:
The back gate is divided into two independent gates: a first back gate positioned under the channel and drift zone, and a second back gate positioned under the extended drain region. This segmentation allows independent control of the electrostatic behavior in different regions, enabling optimization of both breakdown voltage and conduction resistance separately.
Solution Approach 2:
Different doping levels are applied to different regions: the drift zone has medium doping for breakdown voltage, while the extended drain region has light doping to reduce conduction resistance. The dual back gate structure further applies different potentials locally to optimize each region's performance characteristics.
2Reliability
If the drift zone is medium-doped to achieve high breakdown voltage, then the breakdown voltage increases, but the conduction resistance increases due to current flow through this region
Solution Approach 1:
The back gate is segmented into two independent gates: a first back gate under the channel and drift zone for controlling breakdown characteristics, and a second back gate under the extended drain region for controlling conduction resistance. This allows independent optimization of both parameters.
Solution Approach 2:
The extended drain region is lightly-doped to reduce conduction resistance, while the drift zone remains medium-doped for breakdown voltage. The dual back gate structure applies different potentials to different regions to optimize local performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces conduction resistance while maintaining or improving breakdown voltage, enhancing the reliability and efficiency of the transistor without affecting the threshold voltage.
Implementation Method 1
the biasing of these regions is optimized to maintain a reverse-biased junction
Implementation Method 2
the use of a double back gate configuration to independently control the electrostatic behavior and resistivity of the drain extension region
Data Source
AI summary
An extended-drain transistor is formed in a semiconductor layer arranged on one side of an insulating layer with a semiconductor region being arranged on the other side of the insulating layer. The semiconductor region includes a first portion of a first conductivity type arranged in front of the source and at least one larger portion of the gate and a second portion of a second conductivity type arranged in front of at least the larger portion of the extended drain region, each of the first and second portions being coupled to a connection pad.