Extended-Drain Transistors With Field Plate For High Voltage Scaling
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Solution Overview
Problem
Current monolithic integrated circuit (IC) technologies face challenges in supporting low leakage and high voltage devices due to the scaling of high voltage transistors, which reduces the operating window and increases peak electric fields, making it difficult to maintain performance and area scaling as per Moore's Law.
Innovation Solution
The implementation of a field plate electrode over an extended-drain region with a field plate dielectric, positioned closer to the gate electrode than the drain electrode, reduces peak electric fields and mitigates hot carrier effects, while a deep well implant reduces drain-body junction capacitance, enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If lateral scaling is applied to reduce transistor size, then area scaling is improved, but peak electric field increases and high voltage operating window reduces
Solution Approach 1:
The patent extends the drain region laterally beyond the gate width, transitioning from a conventional planar drain to an extended-drain structure. This dimensional extension allows the drain to be positioned in a different spatial relationship to the gate, reducing the peak electric field at the gate-drain interface while maintaining compact area footprint through efficient space utilization in the extended region.
Solution Approach 2:
The patent introduces a field plate electrode as an intermediary structure between the gate and the extended drain region. This field plate acts as a mediator that distributes and reduces the peak electric field, preventing direct high-field stress at the gate-drain junction while enabling the extended-drain configuration to function effectively in reducing overall peak electric field.
2Productivity
If gate length is scaled down, then transistor performance and density are improved, but support for high voltage devices becomes more difficult
Solution Approach 1:
The patent segments the drain structure into multiple regions: a conventional drain region adjacent to the channel and an extended-drain region that protrudes laterally beyond the gate. This segmentation allows the extended region to be optimized for high voltage operation with reduced peak electric field, while the main channel region maintains short gate length for high performance and density. The field plate electrode further segments the electric field distribution.
Solution Approach 2:
The patent applies different structural qualities to different regions: the channel region maintains standard dimensions for high-speed operation, while the extended-drain region is specifically designed with lateral extension and field plate coverage to provide high voltage support. This local differentiation allows simultaneous optimization for both high performance (short channel) and high voltage reliability (extended drain with field plate).
3Area of stationary object
If gate-contact spacing is reduced, then area scaling is improved, but breakdown voltage decreases
Solution Approach 1:
The patent utilizes the lateral dimension by extending the drain region beyond the gate width, creating a three-dimensional spatial arrangement where the extended drain and field plate provide additional breakdown voltage support without increasing the gate-contact spacing in the primary lateral direction. This allows area scaling to be maintained while enhancing voltage tolerance through vertical and lateral field distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the high voltage operating window, reduces drive current degradation, and increases breakdown voltage, facilitating the use of extended-drain transistors in complex monolithic SOC IC designs.
Implementation Method 1
a field plate dielectric laterally disposed between the field plate electrode and the extended-drain region
Implementation Method 2
a deep well implant reduces drain-body junction capacitance
Data Source
Figure 1A~1B
Figure 1C~2A
Figure 2B~2C
AI summary
Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection. In an embodiment, a deep well implant may be disposed between a lightly-doped extended-drain and a substrate to reduce drain-body junction capacitance and improve transistor performance.