Extended Drain Transistor on SOI Substrate for High Voltage Integration
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Solution Overview
Problem
Silicon-on-insulator (SOI) substrates, such as RFSOI and FDSOI, face difficulties in accommodating high voltage (HV) transistors like EDMOS due to their thin surface substrates, requiring complex processing that increases costs.
Innovation Solution
A semiconductor device is designed with a silicon-on-insulator substrate featuring a buried oxide and bulk substrate, including a high voltage device region with a HV gate and source/drain regions, where the HV gate overlaps the bulk substrate and the source/drain regions are positioned to reduce electrical field crowding and simplify integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques are used to integrate HV transistors on SOI substrates, then HV transistor functionality is achieved, but processing complexity and cost increase
Solution Approach 1:
The patent segments the SOI substrate into distinct functional regions: a thin surface substrate region for low-voltage devices and a bulk substrate region for high-voltage devices. The buried oxide layer is selectively removed in the HV device region to expose the bulk substrate, allowing HV transistors to be formed only where needed. This segmentation enables HV functionality without requiring complex processing across the entire substrate.
Solution Approach 2:
The patent applies local quality by providing different substrate thicknesses and structures in different regions. The surface substrate remains thin for LV devices while the bulk substrate is exposed for HV devices. The field oxide thickness is also varied locally - thicker in HV regions for isolation and breakdown voltage, thinner or absent in LV regions for device performance. This local differentiation achieves HV functionality without unnecessarily complicating the entire device structure.
2Reliability
If the HV gate overlaps the bulk substrate, then electrical field distribution is improved, but device structure becomes more complex
Solution Approach 1:
The patent extends the gate structure into the vertical dimension by having the HV gate overlap the bulk substrate beneath the field oxide. This three-dimensional gate configuration allows the gate to control the channel while also managing the electrical field distribution in the vertical direction. The gate sidewalls provide field control in the lateral direction, creating a multi-dimensional field management structure that improves reliability without requiring additional complex components.
Data Source
AI summary
A high voltage (HV) transistor is integrated on a silicon-on-insulator (SOI) substrate. The HV transistor is disposed in a HV device region disposed on a bulk substrate of the SOI substrate. The HV device region includes a top field oxide which includes at least a part of a buried oxide (BOX) of the SOI substrate. A HV gate is disposed in HV region overlapping the HV top field oxide and includes first and second HV gate sidewalls. A drain is disposed on the bulk substrate and displaced from the first HV gate sidewall by the HV top field oxide. A source is disposed on the bulk substrate adjacent to the side of the second HV gate sidewall.