Extended-Drain MOSFET Well Spacing for Lower Output Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Extended-drain metal-oxide-semiconductor devices face increased output capacitance issues as device size shrinks, affecting switching performance due to parasitic gate-drain and gate-source capacitances, which are voltage- and temperature-dependent.
Innovation Solution
A structure for an extended-drain metal-oxide-semiconductor device is formed with a semiconductor substrate, body and drain wells, and a gate electrode, where the drain well is laterally positioned with a spaced relationship to the body well, reducing output capacitance through specific dopant implantation and masking techniques to control conductivity types and concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If device size is reduced, then integration density is improved, but output capacitance increases to unacceptable values
Solution Approach 1:
The drain structure is segmented into a drain region and a drift region separated by a drain-body spacing gap. This segmentation divides the continuous drain into distinct functional zones, allowing the drain region to collect carriers while the drift region handles voltage blocking, thereby reducing output capacitance while maintaining compact device dimensions
Solution Approach 2:
A drain-body spacing gap is introduced as an intermediary space between the drain region and the body well. This gap acts as a mediator that reduces the overlap between drain and gate fields, thereby reducing parasitic capacitance without compromising the device's voltage handling capability or requiring larger overall device size
Data Source
AI summary
Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate, a body well in the semiconductor substrate, a source region in the body well, a drain well in the semiconductor substrate, a drain region in the drain well, and a gate electrode laterally positioned between the source region and the drain region. The drain well includes an edge adjacent to the body well, and the edge of the drain well has a spaced relationship with the body well.


