Extended Floating Gate Flash Cell for High Coupling Ratio
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Solution Overview
Problem
Conventional floating gate transistors in flash memory devices face challenges in achieving a high coupling ratio and minimizing leakage, which are crucial for programming efficiency as cell size shrinks.
Innovation Solution
The implementation of extended floating gates with increased area between the floating gate and the source line, enhancing the capacitance (C1) and thereby increasing the coupling ratio, is achieved through specific processing steps including trench formation, dielectric layer deposition, and patterning of the floating gate and control gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating gate transistor structure is used, then device complexity is reduced, but coupling ratio is insufficient and leakage increases
Solution Approach 1:
The floating gate is extended vertically into trenches below the substrate surface, transitioning from a planar 2D structure to a 3D structure that utilizes the depth dimension. This increases the overlap area between the floating gate and source line without increasing lateral footprint, thereby improving coupling ratio while maintaining compact device layout.
Solution Approach 2:
The floating gate structure is nested within trenches that are formed in the substrate. The extended floating gate portions are positioned within these trenches, creating a nested configuration where the floating gate is embedded in the substrate structure. This increases capacitance coupling while organizing the complex structure in a systematic manner.
2Area of stationary object
If cell size is reduced, then storage density increases, but coupling ratio decreases and leakage increases
Solution Approach 1:
By extending the floating gate vertically into trenches below the substrate surface, the patent increases the effective coupling area without increasing the lateral cell footprint. This allows smaller cell sizes to maintain adequate coupling ratios, enabling higher storage density while preserving programming efficiency.
Solution Approach 2:
The patent changes the geometric parameters of the floating gate by extending its length into the vertical dimension. This parameter change increases the capacitance between the floating gate and source line, improving coupling ratio even as the lateral dimensions of the cell are reduced for higher density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a higher coupling ratio, improving programming efficiency and reducing leakage in flash memory cells, essential for smaller cell sizes.
Implementation Method 1
The coupling ratio, Cr, between the control gate or other secondary gate, and the floating gate is determined by the capacitances of the dielectric between the floating gate and the control gate and also the dielectric between the floating gate and the source line
Data Source
AI summary
Provided is a floating gate flash cell and method for forming the same. The flash includes two floating gate transistors and a common source area therebetween. Each floating gate transistor includes a floating gate having a central portion disposed over a substrate surface and opposed lateral edges that extend into trenches and below the substrate surface. A control gate is disposed over said floating gate with a control gate dielectric between the floating gate and the control gate. The floating gates have side edges that are orthogonal to the opposed lateral edges and a common source area which is a substrate diffusion area, is positioned between respective facing side edges of the floating gates.